[Buildroot] [RFC 0/2] configs: raspberrypi3: fix mismatch cpu arch

[Gaël PORTAY]

Hi all,

The RaspberryPi 3 is powered by a Broadcom BCM2837 which is a 64bits Cortex-A53
ARM processor (armv8).

Currently, BR defines the RPI3 as a simple Cortex-A7 (armv7), which is fair
enough.

The first patch updates the ARM architecture to Cortex-A53 (BR2_cortex_a53=y)
but leave the same 32 bit-length architecture (BR2_arm=y).

BR was compiling and the RPI3 was running fine until I decided to compile
qt5base.

At this stage, GCC (6.3) complains about an unknown attribute:

	tools/qhash.cpp:148:54: error: attribute(target("+crc")) is unknown
	 static uint crc32(const Char *ptr, size_t len, uint h)

According to GCC, the +crc attribute is specific to armv8/AArch64 [1].

Also, according to the ARM (R) C Language Extensions Release 2.0 pdf [2].

	6.5.8 CRC32 Extension
	__ARM_FEATURE_CRC32 is defined to 1 if the CRC32 instructions are
	supported and the intrinsics defined in 9.7 are available. These
	instructions include CRC32B, CRC32H etc. This is only available when
	__ARM_ARCH >= 8

	9.7 CRC32 intrinsics
	CRC32 intrinsics provide direct access to CRC32 instructions
	CRC32{C}{B, H, W, X} in both ARMv8 AArch32 and AArch64 execution states.
	These intrinsics are available when __ARM_FEATURE_CRC32 is defined.

Here is the list of the ARM defines generated by the BR toolchain (w/ BR2_arm=y
and BR2_cortex_a53=y).

	#define __arm__ 1
	#define __ARM_32BIT_STATE 1
	#define __ARM_ARCH 8
	#define __ARM_ARCH_8A__ 1
	#define __ARM_ARCH_EXT_IDIV__ 1
	#define __ARM_ARCH_ISA_ARM 1
	#define __ARM_ARCH_ISA_THUMB 2
	#define __ARM_ARCH_PROFILE 65
	#define __ARM_EABI__ 1
	#define __ARMEL__ 1
	#define __ARM_FEATURE_CLZ 1
	#define __ARM_FEATURE_CRC32 1
	#define __ARM_FEATURE_DSP 1
	#define __ARM_FEATURE_IDIV 1
	#define __ARM_FEATURE_LDREX 15
	#define __ARM_FEATURE_QBIT 1
	#define __ARM_FEATURE_SAT 1
	#define __ARM_FEATURE_SIMD32 1
	#define __ARM_FEATURE_UNALIGNED 1
	#define __ARM_PCS 1
	#define __ARM_SIZEOF_MINIMAL_ENUM 4
	#define __ARM_SIZEOF_WCHAR_T 4

Toolchain seems to be a 32bits (presence of __ARM_32BIT_STATE) and for armv8-a
target (__ARM_ARCH 8, __ARM_ARCH_8A__...).

Because of #define __ARM_FEATURE_CRC32 1, qt5base does not compile (due to the
attribute target=+crc) [3].

Note: If I remove the attribute(target=+crc), the compilation fails at linkage
saying crc32 instructions are bad.

When I force architecture to armv7 (ie. -march=armv7), __ARM_FEATURE_CRC32 is
unset. I assume it compiles.

My understanding is that the crc32 instructions are not available in 32bits
mode.

In this RFC, the second patch tries to fix qt5base. It checks for both defines

        #if defined(__aarch64__) && defined(__ARM_FEATURE_CRC32)

Instead of checking the single define __ARM_FEATURE_CRC32.

I guess my fix is not appropriate. Anyone can tell me what exactly is wrong in
there?
- Maybe I make a confusion between __ARM_32BIT_STATE and AArch32.
- Maybe the toolchain is not properly set using arm/cortex_a53.
- Maybe the points 6.5.8 and 9.7 from [2] are not true.

[1] https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#g_t-march-and--mcpu-Feature-Modifiers
[2] http://infocenter.arm.com/help/topic/com.arm.doc.ihi0053c/IHI0053C_acle_2_0.pdf
[3] https://github.com/qt/qtbase/blob/5.8/src/corelib/tools/qhash.cpp#L140

Regards,
Gaël PORTAY (2):
  configs: raspberrypi3: fix mismatch cpu arch
  qt5base: fix build failure with a 32bit armv8

 configs/raspberrypi3_defconfig                     |  2 +-
 ...01-Fix-ARM32-CRC-build-issue-on-armv8-cpu.patch | 90 ++++++++++++++++++++++
 ...01-Fix-ARM32-CRC-build-issue-on-armv8-cpu.patch |  1 +
 3 files changed, 92 insertions(+), 1 deletion(-)
 create mode 100644 package/qt5/qt5base/5.6.2/0001-Fix-ARM32-CRC-build-issue-on-armv8-cpu.patch
 create mode 120000 package/qt5/qt5base/5.8.0/0001-Fix-ARM32-CRC-build-issue-on-armv8-cpu.patch

PS: Here is the list of the ARM defines if I force -march=armv7.

	#define __arm__ 1
	#define __ARM_32BIT_STATE 1
	#define __ARM_ARCH 7
	#define __ARM_ARCH_7A__ 1
	#define __ARM_ARCH_ISA_ARM 1
	#define __ARM_ARCH_ISA_THUMB 2
	#define __ARM_ARCH_PROFILE 65
	#define __ARM_EABI__ 1
	#define __ARMEL__ 1
	#define __ARM_FEATURE_CLZ 1
	#define __ARM_FEATURE_DSP 1
	#define __ARM_FEATURE_LDREX 15
	#define __ARM_FEATURE_QBIT 1
	#define __ARM_FEATURE_SAT 1
	#define __ARM_FEATURE_SIMD32 1
	#define __ARM_FEATURE_UNALIGNED 1
	#define __ARM_PCS 1
	#define __ARM_SIZEOF_MINIMAL_ENUM 4
	#define __ARM_SIZEOF_WCHAR_T 4

-- 
2.12.1