[Buildroot] [PATCH v3] board/lx2160acex7: new platform
Vincent Jardin
vjardin at free.fr
Thu Sep 4 11:28:54 UTC 2025
Introduce the SolidRun LX2160A-CEX7 platform, which uses the NXP LX2160A
SoC and much of the infrastructure associated with DPAA2 networking.
More details in board/solidrun/lx2160acex7/readme.txt.
ATF, Linux kernel, u-boot patches are imported from:
https://github.com/SolidRun/lx2160a_build/tree/develop-ls-6.6.52-2.2.0/patches
The DTS for the DPL and DPC are imported from:
https://github.com/SolidRun/lx2160a_build/tree/develop-ls-6.6.52-2.2.0/patches/mc-utils
board/solidrun/lx2160acex7/clearfog-cx-s1_8-s2_0-dpc.dts
board/solidrun/lx2160acex7/clearfog-cx-s1_8-s2_0-dpl.dts
but wihtout using a patch of mc-utils since nowadays mc-utils Buildroot
package supports a per board DPL and DPC which is more flexible.
For RCW, it is still a patch on the Buildroot RCW package since:
https://github.com/nxp-qoriq/rcw/
does not support a smooth external RCW with the include dependencies.
Signed-off-by: Vladimir Oltean <olteanv at gmail.com>
Signed-off-by: Vincent Jardin <vjardin at free.fr>
---
.../lx2160acex7/clearfog-cx-s1_8-s2_0-dpc.dts | 109 +
.../lx2160acex7/clearfog-cx-s1_8-s2_0-dpl.dts | 556 +
board/solidrun/lx2160acex7/extlinux.conf | 4 +
board/solidrun/lx2160acex7/genimage.cfg | 54 +
board/solidrun/lx2160acex7/linux.config | 5 +
...pedantic-flag-to-avoid-errors-with-o.patch | 31 +
.../0002-plat-nxp-lx2160a-auto-boot.patch | 204 +
...ccount-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch | 86 +
...ptional-S5-gpio-from-Makefile-consta.patch | 61 +
...flexible-value-for-CONFIG_DDR_NODIMM.patch | 33 +
...ape-mmap-dynamic-configuration-regio.patch | 48 +
...ort-flushing-i2c-bus-before-ddr-init.patch | 384 +
...p-SPD-EEPROM-content-on-debug-builds.patch | 40 +
...error-when-using-non-identical-DIMMs.patch | 35 +
...g-output-for-dimm-parameters-parsed-.patch | 83 +
...-building-without-NXP_NV_SW_MAINT_LA.patch | 49 +
...-boot-without-spi-flash-disable-non-.patch | 33 +
...te-platform-for-solidrun-cex7-module.patch | 423 +
...te-platform-for-solidrun-lx2162a-som.patch | 597 +
...tform-for-solidrun-internal-cex6-eva.patch | 562 +
...ime-flag-to-disable-SYSTEM_OFF-funct.patch | 66 +
...ale-Add-support-for-LX2162-SoM-Clear.patch | 522 +
...-lx2162a-som-add-description-for-rtc.patch | 34 +
...2162a-clearfog-add-alias-for-i2c-bus.patch | 32 +
...a-cex7-add-interrupts-for-rtc-and-et.patch | 39 +
...a-clearfog-itx-enable-pcie-nodes-for.patch | 40 +
...cf2127-clear-minute-second-interrupt.patch | 62 +
...a-extend-32-bit-and-add-64-bit-pci-r.patch | 109 +
...ck-return-value-when-calling-lynx_28.patch | 138 +
...0g-add-support-for-88e2580-multi-gig.patch | 177 +
...reate-driver-for-ds250df4x10-retimer.patch | 502 +
...-clearfog-add-description-for-retime.patch | 52 +
...a-clearfog-cx-add-description-for-re.patch | 81 +
...scription-for-solidrun-lx2160a-cex6-.patch | 568 +
.../0001-lx2162aqds-re-enable-dpmac11.patch | 27 +
...c-jumpc-and-jump-to-pbi-instructions.patch | 55 +
...otlocptr-script-for-automatic-boot-f.patch | 80 +
...ocedure-splitting-sd1-lanes-A-D-40GE.patch | 132 +
...ocedure-converting-sd1-lanes-g-h-fro.patch | 65 +
...ipt-generating-configs-from-template.patch | 70 +
...n-solidrun-lx2160a-cex-7-on-clearfog.patch | 16046 ++++++++++++++++
...n-for-lx2162a-som-and-clearfog-evalu.patch | 720 +
...n-solidrun-internal-lx2160a-cex6-eva.patch | 518 +
...n-solidrun-internal-lx2160acex7-twin.patch | 269 +
...disable-mac7-10-apply-mac5-6-default.patch | 133 +
...ait-100ms-for-Link-Up-in-ls_pcie_g4_.patch | 66 +
...t-100ms-for-Link-Up-in-ls_pcie_probe.patch | 65 +
...-calculation-of-ddr-clock-rate-to-in.patch | 63 +
...able-workaround-for-SPI-erratum-A-05.patch | 103 +
...on-t-fail-boot-when-reading-eeprom-f.patch | 32 +
...upport-specifying-tlv-eeprom-in-DT-a.patch | 57 +
...mpc8xxx-fix-build-on-layerscape-arch.patch | 29 +
...rm-dts-fsl-lx2160a.dtsi-add-pcs-phys.patch | 386 +
...m-dts-fsl-lx2160a.dtsi-add-psci-node.patch | 30 +
...rvell10g-add-support-for-88e2580-phy.patch | 43 +
...d-solidrun-lx2160-cex7-board-support.patch | 1753 ++
...x2160cex7-add-support-for-lx2162-som.patch | 164 +
...x2160cex7-add-support-for-lx2162-cle.patch | 442 +
...x2160cex7-add-support-for-clearfog-c.patch | 238 +
...x2160cex7-configure-fan-controller-d.patch | 138 +
...x2160cex7-fix-read-rcw-from-dcsr-mem.patch | 48 +
...x2160cex7-add-support-for-half-twins.patch | 634 +
...-copy-optee-to-OS-DTB-regardless-if-.patch | 56 +
...x2160cex7-fix-xspi-flash-compatible-.patch | 30 +
...x2160acex7-fix-serdes-lane-dpmac-swa.patch | 124 +
...-adding-optee-subnode-if-not-present.patch | 31 +
...x2160cex7-setup-retimers-for-active-.patch | 513 +
...n-disable-some-unused-config-options.patch | 66 +
...x2160acex7-fix-various-mistakes-in-s.patch | 703 +
...x2160acex7-disable-disabled-ports-pr.patch | 367 +
.../0026-cmd-add-ds250dfx10-control.patch | 994 +
...dd-prbs-validation-command-for-timed.patch | 938 +
board/solidrun/lx2160acex7/post-build.sh | 8 +
board/solidrun/lx2160acex7/readme.txt | 136 +
.../udev/rules.d/74-dpaa2-networking.rules | 12 +
.../lx2160acex7/u-boot-environment-sd.txt | 96 +
configs/solidrun_lx2160acex7_defconfig | 53 +
77 files changed, 32352 insertions(+)
create mode 100644 board/solidrun/lx2160acex7/clearfog-cx-s1_8-s2_0-dpc.dts
create mode 100644 board/solidrun/lx2160acex7/clearfog-cx-s1_8-s2_0-dpl.dts
create mode 100644 board/solidrun/lx2160acex7/extlinux.conf
create mode 100644 board/solidrun/lx2160acex7/genimage.cfg
create mode 100644 board/solidrun/lx2160acex7/linux.config
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0001-fiptool-disable-pedantic-flag-to-avoid-errors-with-o.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0002-plat-nxp-lx2160a-auto-boot.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0003-dcfg-Take-into-account-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0004-lx2160a-assert-optional-S5-gpio-from-Makefile-consta.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0005-lx2160a-support-flexible-value-for-CONFIG_DDR_NODIMM.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0006-plat-nxp-layerscape-mmap-dynamic-configuration-regio.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0007-lx2160a-support-flushing-i2c-bus-before-ddr-init.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0008-nxp-ddr-dump-SPD-EEPROM-content-on-debug-builds.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0009-nxp-ddr-disarm-error-when-using-non-identical-DIMMs.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0010-nxp-ddr-add-debug-output-for-dimm-parameters-parsed-.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0011-plat-lx2160a-fix-building-without-NXP_NV_SW_MAINT_LA.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0012-plat-lx2160a-fix-boot-without-spi-flash-disable-non-.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0013-add-separate-platform-for-solidrun-cex7-module.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0014-add-separate-platform-for-solidrun-lx2162a-som.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0015-add-separate-platform-for-solidrun-internal-cex6-eva.patch
create mode 100644 board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0016-psci-add-build-time-flag-to-disable-SYSTEM_OFF-funct.patch
create mode 100644 board/solidrun/lx2160acex7/patches/linux/0001-arm64-dts-freescale-Add-support-for-LX2162-SoM-Clear.patch
create mode 100644 board/solidrun/lx2160acex7/patches/linux/0002-arm64-dts-fsl-lx2162a-som-add-description-for-rtc.patch
create mode 100644 board/solidrun/lx2160acex7/patches/linux/0003-arm64-dts-fsl-lx2162a-clearfog-add-alias-for-i2c-bus.patch
create mode 100644 board/solidrun/lx2160acex7/patches/linux/0004-arm64-dts-lx2160a-cex7-add-interrupts-for-rtc-and-et.patch
create mode 100644 board/solidrun/lx2160acex7/patches/linux/0005-arm64-dts-lx2160a-clearfog-itx-enable-pcie-nodes-for.patch
create mode 100644 board/solidrun/lx2160acex7/patches/linux/0006-rtc-pcf2127-clear-minute-second-interrupt.patch
create mode 100644 board/solidrun/lx2160acex7/patches/linux/0007-arm64-dts-lx2160a-extend-32-bit-and-add-64-bit-pci-r.patch
create mode 100644 board/solidrun/lx2160acex7/patches/linux/0008-phy-lynx-28g-check-return-value-when-calling-lynx_28.patch
create mode 100644 board/solidrun/lx2160acex7/patches/linux/0009-net-phy-marvell10g-add-support-for-88e2580-multi-gig.patch
create mode 100644 board/solidrun/lx2160acex7/patches/linux/0010-net-phy-create-driver-for-ds250df4x10-retimer.patch
create mode 100644 board/solidrun/lx2160acex7/patches/linux/0011-arm64-dts-lx2162-clearfog-add-description-for-retime.patch
create mode 100644 board/solidrun/lx2160acex7/patches/linux/0012-arm64-dts-lx2160a-clearfog-cx-add-description-for-re.patch
create mode 100644 board/solidrun/lx2160acex7/patches/linux/0013-arm64-dts-add-description-for-solidrun-lx2160a-cex6-.patch
create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0001-lx2162aqds-re-enable-dpmac11.patch
create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0002-add-loadc-jumpc-and-jump-to-pbi-instructions.patch
create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0003-lx2160asi-add-bootlocptr-script-for-automatic-boot-f.patch
create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0004-lx2160asi-add-procedure-splitting-sd1-lanes-A-D-40GE.patch
create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0005-lx2160asi-add-procedure-converting-sd1-lanes-g-h-fro.patch
create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0006-solidrun-add-script-generating-configs-from-template.patch
create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0007-add-configuration-solidrun-lx2160a-cex-7-on-clearfog.patch
create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0008-add-configuration-for-lx2162a-som-and-clearfog-evalu.patch
create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0009-add-configuration-solidrun-internal-lx2160a-cex6-eva.patch
create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0010-add-configuration-solidrun-internal-lx2160acex7-twin.patch
create mode 100644 board/solidrun/lx2160acex7/patches/qoriq-rcw/0011-lx2162asom_rev2-disable-mac7-10-apply-mac5-6-default.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0001-pci-ls_pcie_g4-Wait-100ms-for-Link-Up-in-ls_pcie_g4_.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0002-pci-ls_pcie-Wait-100ms-for-Link-Up-in-ls_pcie_probe.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0003-fsl-lsch3-update-calculation-of-ddr-clock-rate-to-in.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0004-armv8-lx2160a-enable-workaround-for-SPI-erratum-A-05.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0005-cmd-tlv_eeprom-don-t-fail-boot-when-reading-eeprom-f.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0006-cmd-tlv_eeprom-support-specifying-tlv-eeprom-in-DT-a.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0007-gpio-mpc8xxx-fix-build-on-layerscape-arch.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0008-arch-arm-dts-fsl-lx2160a.dtsi-add-pcs-phys.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0009-arch-arm-dts-fsl-lx2160a.dtsi-add-psci-node.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0010-net-phy-marvell10g-add-support-for-88e2580-phy.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0011-add-solidrun-lx2160-cex7-board-support.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0012-board-solidrun-lx2160cex7-add-support-for-lx2162-som.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0013-board-solidrun-lx2160cex7-add-support-for-lx2162-cle.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0014-board-solidrun-lx2160cex7-add-support-for-clearfog-c.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0015-board-solidrun-lx2160cex7-configure-fan-controller-d.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0016-board-solidrun-lx2160cex7-fix-read-rcw-from-dcsr-mem.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0017-board-solidrun-lx2160cex7-add-support-for-half-twins.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0018-lib-optee-always-copy-optee-to-OS-DTB-regardless-if-.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0019-board-solidrun-lx2160cex7-fix-xspi-flash-compatible-.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0020-board-solidrun-lx2160acex7-fix-serdes-lane-dpmac-swa.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0021-lib-optee-fix-adding-optee-subnode-if-not-present.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0022-board-solidrun-lx2160cex7-setup-retimers-for-active-.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0023-board-solidrun-disable-some-unused-config-options.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0024-board-solidrun-lx2160acex7-fix-various-mistakes-in-s.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0025-board-solidrun-lx2160acex7-disable-disabled-ports-pr.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0026-cmd-add-ds250dfx10-control.patch
create mode 100644 board/solidrun/lx2160acex7/patches/uboot/0027-cmd-ds250dfx10-add-prbs-validation-command-for-timed.patch
create mode 100755 board/solidrun/lx2160acex7/post-build.sh
create mode 100644 board/solidrun/lx2160acex7/readme.txt
create mode 100644 board/solidrun/lx2160acex7/rootfs_overlay/etc/udev/rules.d/74-dpaa2-networking.rules
create mode 100644 board/solidrun/lx2160acex7/u-boot-environment-sd.txt
create mode 100644 configs/solidrun_lx2160acex7_defconfig
diff --git a/board/solidrun/lx2160acex7/clearfog-cx-s1_8-s2_0-dpc.dts b/board/solidrun/lx2160acex7/clearfog-cx-s1_8-s2_0-dpc.dts
new file mode 100644
index 0000000000..54943fbce8
--- /dev/null
+++ b/board/solidrun/lx2160acex7/clearfog-cx-s1_8-s2_0-dpc.dts
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2018 NXP
+ * Copyright 2022 Josua Mayer <josua at solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This DPC configures SolidRun Clearfog-CX with 8x10Gbps SerDes & 1Gbps RGMII ports.
+ */
+
+/dts-v1/;
+
+/ {
+ resources {
+ icid_pools {
+
+ icid_pool at 1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ timestamp = "LOG_TIMESTAMP_ON"; /* "LOG_TIMESTAMP_OFF" */
+ };
+
+ console {
+ mode = "CONSOLE_MODE_ON";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <32>;
+ };
+ };
+
+ board_info {
+ ports {
+ mac at 3 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac at 4 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac at 5 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac at 6 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac at 7 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac at 8 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac at 9 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac at 10 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac at 17 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/board/solidrun/lx2160acex7/clearfog-cx-s1_8-s2_0-dpl.dts b/board/solidrun/lx2160acex7/clearfog-cx-s1_8-s2_0-dpl.dts
new file mode 100644
index 0000000000..e91f837cae
--- /dev/null
+++ b/board/solidrun/lx2160acex7/clearfog-cx-s1_8-s2_0-dpl.dts
@@ -0,0 +1,556 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+/ {
+ dpl-version = <10>;
+ /*****************************************************************
+ * Containers
+ *****************************************************************/
+ containers {
+
+ dprc at 1 {
+ compatible = "fsl,dprc";
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+
+ objects {
+
+ /* -------------- DPBPs --------------*/
+ obj_set at dpbp {
+ type = "dpbp";
+ ids = <0 >;
+ };
+
+ /* -------------- DPCONs --------------*/
+ obj_set at dpcon {
+ type = "dpcon";
+ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >;
+ };
+
+ /* -------------- DPIOs --------------*/
+ obj_set at dpio {
+ type = "dpio";
+ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >;
+ };
+
+ /* -------------- DPMACs --------------*/
+ obj_set at dpmac {
+ type = "dpmac";
+ ids = <3 4 5 6 7 8 9 10 17 >;
+ };
+
+ /* -------------- DPMCPs --------------*/
+ obj_set at dpmcp {
+ type = "dpmcp";
+ ids = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 >;
+ };
+
+ /* -------------- DPNIs --------------*/
+ obj_set at dpni {
+ type = "dpni";
+ ids = <0 >;
+ };
+
+ /* -------------- DPRTCs --------------*/
+ obj_set at dprtc {
+ type = "dprtc";
+ ids = <0 >;
+ };
+
+ /* -------------- DPSECIs --------------*/
+ obj_set at dpseci {
+ type = "dpseci";
+ ids = <0 >;
+ };
+ };
+ };
+ };
+
+ /*****************************************************************
+ * Objects
+ *****************************************************************/
+ objects {
+
+ dpbp at 0 {
+ compatible = "fsl,dpbp";
+ };
+
+ dpcon at 0 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 1 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 2 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 3 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 4 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 5 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 6 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 7 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 8 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 9 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 10 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 11 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 12 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 13 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 14 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon at 15 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpio at 0 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 1 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 2 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 3 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 4 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 5 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 6 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 7 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 8 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 9 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 10 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 11 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 12 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 13 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 14 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio at 15 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpmac at 3 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac at 4 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac at 5 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac at 6 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac at 7 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac at 8 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac at 9 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac at 10 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac at 17 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmcp at 1 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 2 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 3 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 4 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 5 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 6 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 7 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 8 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 9 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 10 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 11 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 12 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 13 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 14 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 15 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 16 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 17 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 18 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 19 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 20 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 21 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 22 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 23 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 24 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 25 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 26 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 27 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 28 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 29 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 30 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 31 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 32 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 33 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 34 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 35 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 36 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 37 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 38 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 39 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 40 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 41 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 42 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 43 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 44 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 45 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 46 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 47 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 48 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 49 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 50 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 51 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp at 52 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpni at 0 {
+ compatible = "fsl,dpni";
+ type = "DPNI_TYPE_NIC";
+ num_queues = <16>;
+ num_tcs = <1>;
+ num_cgs = <1>;
+ mac_filter_entries = <16>;
+ vlan_filter_entries = <0>;
+ fs_entries = <64>;
+ qos_entries = <0>;
+ dist_key_size = <56>;
+ };
+
+ dprtc at 0 {
+ compatible = "fsl,dprtc";
+ };
+
+ dpseci at 0 {
+ compatible = "fsl,dpseci";
+ priorities = <1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1>;
+ };
+ };
+
+ /*****************************************************************
+ * Connections
+ *****************************************************************/
+ connections {
+
+ connection at 1{
+ endpoint1 = "dpni at 0";
+ endpoint2 = "dpmac at 17";
+ };
+ };
+};
diff --git a/board/solidrun/lx2160acex7/extlinux.conf b/board/solidrun/lx2160acex7/extlinux.conf
new file mode 100644
index 0000000000..018f35a2ec
--- /dev/null
+++ b/board/solidrun/lx2160acex7/extlinux.conf
@@ -0,0 +1,4 @@
+label Solidrun LX2160A COM Express Type 7
+ kernel /boot/Image
+ devicetree /boot/fsl-lx2160a-clearfog-cx.dtb
+ append root=PARTUUID=%PARTUUID% rw rootwait cma=256M
diff --git a/board/solidrun/lx2160acex7/genimage.cfg b/board/solidrun/lx2160acex7/genimage.cfg
new file mode 100644
index 0000000000..210403469d
--- /dev/null
+++ b/board/solidrun/lx2160acex7/genimage.cfg
@@ -0,0 +1,54 @@
+image sdcard.img {
+ hdimage {
+ partition-table-type = "gpt"
+ gpt-location = 6M
+ }
+
+ partition rcw {
+ offset = 4K
+ in-partition-table = "no"
+ image = "bl2_sd.pbl"
+ }
+
+ partition u-boot {
+ offset = 1M
+ in-partition-table = "no"
+ image = "fip.bin"
+ }
+
+ partition u-boot-environment {
+ in-partition-table = "no"
+ image = "uboot-env.bin"
+ offset = 5M
+ }
+
+ partition ddr-phy {
+ in-partition-table = "no"
+ image = "fip_ddr.bin"
+ offset = 8M
+ }
+
+ partition dpaa2-mc {
+ in-partition-table = "no"
+ image = "mc.itb"
+ offset = 10M
+ }
+
+ partition dpaa2-dpl {
+ in-partition-table = "no"
+ image = "clearfog-cx-s1_8-s2_0-dpl.dtb"
+ offset = 13M
+ }
+
+ partition dpaa2-dpc {
+ in-partition-table = "no"
+ image = "clearfog-cx-s1_8-s2_0-dpc.dtb"
+ offset = 14M
+ }
+
+ partition rootfs {
+ bootable = "true"
+ image = "rootfs.ext4"
+ partition-uuid = %PARTUUID%
+ }
+}
diff --git a/board/solidrun/lx2160acex7/linux.config b/board/solidrun/lx2160acex7/linux.config
new file mode 100644
index 0000000000..8b8ad73692
--- /dev/null
+++ b/board/solidrun/lx2160acex7/linux.config
@@ -0,0 +1,5 @@
+CONFIG_BLK_DEV_NVME=y
+CONFIG_PMBUS=y
+CONFIG_SENSORS_AMC6821=y
+CONFIG_SENSORS_LTC2978=y
+CONFIG_SENSORS_LTC2978_REGULATOR=y
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0001-fiptool-disable-pedantic-flag-to-avoid-errors-with-o.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0001-fiptool-disable-pedantic-flag-to-avoid-errors-with-o.patch
new file mode 100644
index 0000000000..3be0eda128
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0001-fiptool-disable-pedantic-flag-to-avoid-errors-with-o.patch
@@ -0,0 +1,31 @@
+From 16002464625b0841b4adc537e53a5fb357ff907c Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Mon, 28 Jul 2025 12:37:46 +0200
+Subject: [PATCH 01/15] fiptool: disable pedantic flag to avoid errors with
+ older libc
+
+This change disarms soime pedantic errors encountered when using a new
+gcc-13 with older system glibc headers. In particular when using yocto
+with a buildtools tarball thius situation can occur.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ tools/fiptool/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
+index fda7c7795..3c0084a16 100644
+--- a/tools/fiptool/Makefile
++++ b/tools/fiptool/Makefile
+@@ -16,7 +16,7 @@ V ?= 0
+ STATIC ?= 0
+
+ override CPPFLAGS += -D_GNU_SOURCE -D_XOPEN_SOURCE=700
+-HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99
++HOSTCCFLAGS := -Wall -Werror -std=c99
+ ifeq (${DEBUG},1)
+ HOSTCCFLAGS += -g -O0 -DDEBUG
+ else
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0002-plat-nxp-lx2160a-auto-boot.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0002-plat-nxp-lx2160a-auto-boot.patch
new file mode 100644
index 0000000000..b38712542b
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0002-plat-nxp-lx2160a-auto-boot.patch
@@ -0,0 +1,204 @@
+From d88ed58278a43ef670d125fce416c04c40bdbc70 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh at solid-run.com>
+Date: Sun, 28 Nov 2021 14:00:07 +0200
+Subject: [PATCH 02/15] plat/nxp: lx2160a auto boot
+
+This patch adds support to patch RCW that already has SD/eMMC/SPI boot
+support embedded with conditional load and jump.
+The idea is to look for SD/eMMC/SPI boot, and modify src/dst/size
+address with the correct values; rather than adding blockread at the end
+of RCW code.
+
+With this patch images are unified and can be used to boot from SD /
+eMMC and SPI.
+
+Signed-off-by: Rabeeh Khoury <rabeeh at solid-run.com>
+---
+ .../plat_make_helper/plat_common_def.mk | 5 ++
+ plat/nxp/soc-lx2160a/soc.mk | 5 ++
+ tools/nxp/create_pbl/create_pbl.c | 74 ++++++++++++++++---
+ 3 files changed, 74 insertions(+), 10 deletions(-)
+
+diff --git a/plat/nxp/common/plat_make_helper/plat_common_def.mk b/plat/nxp/common/plat_make_helper/plat_common_def.mk
+index 86dacf83d..a1038a073 100644
+--- a/plat/nxp/common/plat_make_helper/plat_common_def.mk
++++ b/plat/nxp/common/plat_make_helper/plat_common_def.mk
+@@ -91,6 +91,11 @@ define add_boot_mode_define
+ else ifeq ($(1),flexspi_nor)
+ $$(eval $$(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2))
+ $$(eval $$(call add_define,FLEXSPI_NOR_BOOT))
++ else ifeq ($(1),auto)
++ $$(eval $$(call SET_FLAG,SD_MMC_NEEDED,BL2))
++ $$(eval $$(call add_define,EMMC_BOOT))
++ $$(eval $$(call SET_FLAG,XSPI_NEEDED,BL2))
++ $$(eval $$(call add_define,FLEXSPI_NOR_BOOT))
+ else
+ $$(error $(PLAT) Cannot Support Boot Mode: $(BOOT_MODE))
+ endif
+diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk
+index 239442c20..a72b4113d 100644
+--- a/plat/nxp/soc-lx2160a/soc.mk
++++ b/plat/nxp/soc-lx2160a/soc.mk
+@@ -82,6 +82,11 @@ else
+ ifeq (${BOOT_MODE}, emmc)
+ $(eval $(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
+ $(eval $(call add_define,EMMC_BOOT))
++else ifeq (${BOOT_MODE}, auto)
++$(eval $(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
++$(eval $(call add_define,EMMC_BOOT))
++$(eval $(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2))
++$(eval $(call add_define,FLEXSPI_NOR_BOOT))
+ else
+ $(error Un-supported Boot Mode = ${BOOT_MODE})
+ endif
+diff --git a/tools/nxp/create_pbl/create_pbl.c b/tools/nxp/create_pbl/create_pbl.c
+index c277e391a..ddda4dc68 100644
+--- a/tools/nxp/create_pbl/create_pbl.c
++++ b/tools/nxp/create_pbl/create_pbl.c
+@@ -66,6 +66,7 @@ typedef enum {
+ FLXSPI_NOR_BOOT,
+ FLXSPI_NAND_BOOT,
+ FLXSPI_NAND4K_BOOT,
++ AUTO_BOOT,
+ MAX_BOOT /* must be last item in list */
+ } boot_src_t;
+
+@@ -140,6 +141,7 @@ char *boot_src_string[] = {
+ "FLXSPI_NOR_BOOT",
+ "FLXSPI_NAND_BOOT",
+ "FLXSPI_NAND4K_BOOT",
++ "AUTO_BOOT",
+ };
+
+ enum stop_command {
+@@ -193,7 +195,7 @@ struct pbl_image {
+ #define SOC_LS2088 2088
+ #define SOC_LX2160 2160
+
+-static uint32_t pbl_size;
++static uint32_t pbl_size = 0;
+ bool sb_flag;
+
+ /***************************************************************************
+@@ -703,6 +705,8 @@ int main(int argc, char **argv)
+ int ret = FAILURE;
+ bool bootptr_flag = false;
+ enum stop_command flag_stop_cmd = CRC_STOP_COMMAND;
++ int skip = 0;
++ uint32_t saved_src;
+
+ /* Initializing the global structure to zero. */
+ memset(&pblimg, 0x0, sizeof(struct pbl_image));
+@@ -802,6 +806,8 @@ int main(int argc, char **argv)
+ pblimg.boot_src = FLXSPI_NAND_BOOT;
+ } else if (strcmp(optarg, "flexspi_nand2k") == 0) {
+ pblimg.boot_src = FLXSPI_NAND4K_BOOT;
++ } else if (strcmp(optarg, "auto") == 0) {
++ pblimg.boot_src = AUTO_BOOT;
+ } else {
+ printf("CMD Error: Invalid boot source.\n");
+ goto exit_main;
+@@ -909,13 +915,14 @@ int main(int argc, char **argv)
+ printf("%s: Error reading PBI Cmd.\n", __func__);
+ goto exit_main;
+ }
++ saved_src = pblimg.src_addr;
+ while (word != 0x808f0000 && word != 0x80ff0000) {
+ pbl_size++;
+ /* 11th words in RCW has PBL length. Update it
+ * with new length. 2 commands get added
+ * Block copy + CCSR Write/CSF header write
+ */
+- if (pbl_size == 11) {
++ if ((pbl_size == 11) && (pblimg.boot_src != AUTO_BOOT)) {
+ word_1 = (word & PBI_LEN_MASK)
+ + (PBI_LEN_ADD << 20);
+ word = word & ~PBI_LEN_MASK;
+@@ -933,8 +940,50 @@ int main(int argc, char **argv)
+ goto exit_main;
+ }
+ }
+- if (fwrite(&word, sizeof(word), NUM_MEM_BLOCK,
+- fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
++ if (pblimg.boot_src == AUTO_BOOT) {
++ if (word == 0x80000008) {
++ printf ("Found SD boot at %d\n",pbl_size);
++ pblimg.boot_src = SD_BOOT;
++ add_blk_cpy_cmd(fp_rcw_pbi_op, args);
++ skip = 4; // skip original blockcopy
++ pblimg.boot_src = AUTO_BOOT;
++ pblimg.src_addr = saved_src;
++ if (bootptr_flag == true) {
++ add_boot_ptr_cmd(fp_rcw_pbi_op);
++ skip += 2; // skip original bootlocptr write (low byte only)
++ printf("added bootptr\n");
++ }
++ }
++ if (word == 0x80000009) {
++ printf ("Found eMMC boot at %d\n",pbl_size);
++ pblimg.boot_src = EMMC_BOOT;
++ add_blk_cpy_cmd(fp_rcw_pbi_op, args);
++ skip = 4; // skip original blockcopy
++ pblimg.boot_src = AUTO_BOOT;
++ pblimg.src_addr = saved_src;
++ if (bootptr_flag == true) {
++ add_boot_ptr_cmd(fp_rcw_pbi_op);
++ skip += 2; // skip original bootlocptr write (low byte only)
++ printf("added bootptr\n");
++ }
++ }
++ if (word == 0x8000000f) {
++ printf ("Found SPI boot at %d\n",pbl_size);
++ pblimg.boot_src = FLXSPI_NOR_BOOT;
++ add_blk_cpy_cmd(fp_rcw_pbi_op, args);
++ skip = 4; // skip original blockcopy
++ pblimg.boot_src = AUTO_BOOT;
++ pblimg.src_addr = saved_src;
++ if (bootptr_flag == true) {
++ add_boot_ptr_cmd(fp_rcw_pbi_op);
++ skip += 2; // skip original bootlocptr write (low byte only)
++ printf("added bootptr\n");
++ }
++ }
++ }
++ if (!skip &&
++ (fwrite(&word, sizeof(word), NUM_MEM_BLOCK,
++ fp_rcw_pbi_op) != NUM_MEM_BLOCK)) {
+ printf("%s: [CH3] Error in Writing PBI Words\n",
+ __func__);
+ goto exit_main;
+@@ -951,8 +1000,11 @@ int main(int argc, char **argv)
+ } else if (word == STOP_CMD_ARM_CH3) {
+ flag_stop_cmd = STOP_COMMAND;
+ }
++
++ if (skip)
++ skip--;
+ }
+- if (bootptr_flag == true) {
++ if ((pblimg.boot_src != AUTO_BOOT) && (bootptr_flag == true)) {
+ /* Add command to set boot_loc ptr */
+ ret = add_boot_ptr_cmd(fp_rcw_pbi_op);
+ if (ret != SUCCESS) {
+@@ -963,11 +1015,13 @@ int main(int argc, char **argv)
+ }
+
+ /* Write acs write commands to output file */
+- ret = add_blk_cpy_cmd(fp_rcw_pbi_op, args);
+- if (ret != SUCCESS) {
+- printf("%s: Function add_blk_cpy_cmd return failure.\n",
+- __func__);
+- goto exit_main;
++ if (pblimg.boot_src != AUTO_BOOT) {
++ ret = add_blk_cpy_cmd(fp_rcw_pbi_op, args);
++ if (ret != SUCCESS) {
++ printf("%s: Function add_blk_cpy_cmd return failure.\n",
++ __func__);
++ goto exit_main;
++ }
+ }
+
+ /* Add stop command after adding pbi commands */
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0003-dcfg-Take-into-account-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0003-dcfg-Take-into-account-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch
new file mode 100644
index 0000000000..d379ef2acb
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0003-dcfg-Take-into-account-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch
@@ -0,0 +1,86 @@
+From 938dddf91666d98de8f1bbea9d9f5f5d653a3b7c Mon Sep 17 00:00:00 2001
+From: Jon Nettleton <jon at solid-run.com>
+Date: Tue, 8 Oct 2024 04:56:45 +0200
+Subject: [PATCH 03/15] dcfg: Take into account MEM_PLL_CFG_SHIFT for ddr
+ frequency
+
+The base ddr clock frequency is 1/4 the speed of the final
+ddr clock frequency. By default the RCW config is setting
+the CFG_SHIFT to be a 1/4 divider of the memory speed,
+i.e. 3200 / 4 (800MHz). The parent DDRCLK is 100MHz so PLL_RAT
+needs to be rounded to 100MHz. However using a divider of / 3 for
+a lower speed always us to match industry standard ddr4 speeds
+2666 and 2933 (2000 / 3 * 4 = 2666.67)
+
+This patch takes into account the PLL_CFG_SHIFT divider so these
+speeds can be configured in the RCW and then updates the helper
+function that reports ddr_clk_freq to properly multiply the
+clock fed into the DDRC * 4 to properly reflect the actual MTs
+that the memory is being configured for.
+
+Signed-off-by: Jon Nettleton <jon at solid-run.com>
+---
+ drivers/nxp/dcfg/dcfg.c | 6 ++++++
+ drivers/nxp/ddr/nxp-ddr/utility.c | 6 +++---
+ include/drivers/nxp/dcfg/dcfg_lsch3.h | 4 ++++
+ 3 files changed, 13 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/nxp/dcfg/dcfg.c b/drivers/nxp/dcfg/dcfg.c
+index e5c4db437..4a5820a64 100644
+--- a/drivers/nxp/dcfg/dcfg.c
++++ b/drivers/nxp/dcfg/dcfg.c
+@@ -104,9 +104,15 @@ int get_clocks(struct sysinfo *sys)
+ sys->freq_ddr_pll0 *= (gur_in32(rcwsr0) >>
+ RCWSR0_MEM_PLL_RAT_SHIFT) &
+ RCWSR0_MEM_PLL_RAT_MASK;
++ sys->freq_ddr_pll0 /= ((gur_in32(rcwsr0) >>
++ RCWSR0_MEM_PLL_CFG_SHIFT) &
++ RCWSR0_MEM_PLL_CFG_MASK) + 1;
+ sys->freq_ddr_pll1 *= (gur_in32(rcwsr0) >>
+ RCWSR0_MEM2_PLL_RAT_SHIFT) &
+ RCWSR0_MEM2_PLL_RAT_MASK;
++ sys->freq_ddr_pll1 /= ((gur_in32(rcwsr0) >>
++ RCWSR0_MEM2_PLL_CFG_SHIFT) &
++ RCWSR0_MEM2_PLL_CFG_MASK) + 1;
+ if (sys->freq_platform == 0) {
+ return 1;
+ } else {
+diff --git a/drivers/nxp/ddr/nxp-ddr/utility.c b/drivers/nxp/ddr/nxp-ddr/utility.c
+index b6dffc872..3920b4488 100644
+--- a/drivers/nxp/ddr/nxp-ddr/utility.c
++++ b/drivers/nxp/ddr/nxp-ddr/utility.c
+@@ -47,11 +47,11 @@ unsigned long get_ddr_freq(struct sysinfo *sys, int ctrl_num)
+
+ switch (ctrl_num) {
+ case 0:
+- return sys->freq_ddr_pll0;
++ return sys->freq_ddr_pll0 * 4;
+ case 1:
+- return sys->freq_ddr_pll0;
++ return sys->freq_ddr_pll0 * 4;
+ case 2:
+- return sys->freq_ddr_pll1;
++ return sys->freq_ddr_pll1 * 4;
+ }
+
+ return 0;
+diff --git a/include/drivers/nxp/dcfg/dcfg_lsch3.h b/include/drivers/nxp/dcfg/dcfg_lsch3.h
+index cde86fe19..f9409d1a7 100644
+--- a/include/drivers/nxp/dcfg/dcfg_lsch3.h
++++ b/include/drivers/nxp/dcfg/dcfg_lsch3.h
+@@ -53,8 +53,12 @@
+ #define RCWSR0_OFFSET 0x100
+ #define RCWSR0_SYS_PLL_RAT_SHIFT 2
+ #define RCWSR0_SYS_PLL_RAT_MASK 0x1f
++#define RCWSR0_MEM_PLL_CFG_SHIFT 8
++#define RCWSR0_MEM_PLL_CFG_MASK 0x3
+ #define RCWSR0_MEM_PLL_RAT_SHIFT 10
+ #define RCWSR0_MEM_PLL_RAT_MASK 0x3f
++#define RCWSR0_MEM2_PLL_CFG_SHIFT 16
++#define RCWSR0_MEM2_PLL_CFG_MASK 0x3
+ #define RCWSR0_MEM2_PLL_RAT_SHIFT 18
+ #define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
+
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0004-lx2160a-assert-optional-S5-gpio-from-Makefile-consta.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0004-lx2160a-assert-optional-S5-gpio-from-Makefile-consta.patch
new file mode 100644
index 0000000000..f98bdd9fba
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0004-lx2160a-assert-optional-S5-gpio-from-Makefile-consta.patch
@@ -0,0 +1,61 @@
+From 36bf5eae8356d2c89047e8b5f751d6f2c2d922a1 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh at solid-run.com>
+Date: Sun, 28 Nov 2021 13:33:10 +0200
+Subject: [PATCH 04/15] lx2160a: assert optional S5 gpio from Makefile constant
+
+GPIO address and number for S5 are specific per board and should not be
+set globally across lx2160.
+
+Add support for setting gpio address and number form platform.mk, into
+soc.mk:
+
+- LX2160A_S5_GPIO_ADDR: gpio value register address
+- LX2160A_S5_GPIO: gpio number
+
+This feature can be enabled for individual boards by setting a non-zero
+address in platform.mk file, before including soc.mk.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ plat/nxp/soc-lx2160a/aarch64/lx2160a.S | 8 ++++++++
+ plat/nxp/soc-lx2160a/soc.mk | 8 ++++++++
+ 2 files changed, 16 insertions(+)
+
+diff --git a/plat/nxp/soc-lx2160a/aarch64/lx2160a.S b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S
+index cc679f2ba..67ade7b66 100644
+--- a/plat/nxp/soc-lx2160a/aarch64/lx2160a.S
++++ b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S
+@@ -563,6 +563,14 @@ endfunc _soc_sys_reset
+ */
+ func _soc_sys_off
+
++#if defined(CONFIG_LX2160A_S5_GPIO_ADDR) && defined(CONFIG_LX2160A_S5_GPIO)
++ /* assert s5 gpio */
++ mov x3, # CONFIG_LX2160A_S5_GPIO_ADDR
++ ldr w1, [x3]
++ orr w1, w1, # 1 << (31 - CONFIG_LX2160A_S5_GPIO)
++ str w1, [x3]
++#endif
++
+ /* disable sec, QBman, spi and qspi */
+ ldr x2, =NXP_DCFG_ADDR
+ ldr x0, =DCFG_DEVDISR1_OFFSET
+diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk
+index a72b4113d..20e64753c 100644
+--- a/plat/nxp/soc-lx2160a/soc.mk
++++ b/plat/nxp/soc-lx2160a/soc.mk
+@@ -177,3 +177,11 @@ include ${PLAT_PATH}/common/setup/common.mk
+
+ # Adding source files to generate separate DDR FIP image
+ include ${PLAT_SOC_PATH}/ddr_fip.mk
++
++# S5 GPIO (optional)
++LX2160A_S5_GPIO_ADDR ?= 0
++LX2160A_S5_GPIO ?= 0
++ifneq (${LX2160A_S5_GPIO_ADDR},0)
++$(eval $(call add_define_val,CONFIG_LX2160A_S5_GPIO_ADDR,$(LX2160A_S5_GPIO_ADDR)))
++$(eval $(call add_define_val,CONFIG_LX2160A_S5_GPIO,$(LX2160A_S5_GPIO)))
++endif
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0005-lx2160a-support-flexible-value-for-CONFIG_DDR_NODIMM.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0005-lx2160a-support-flexible-value-for-CONFIG_DDR_NODIMM.patch
new file mode 100644
index 0000000000..202eebb549
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0005-lx2160a-support-flexible-value-for-CONFIG_DDR_NODIMM.patch
@@ -0,0 +1,33 @@
+From 5f8f78883f22663b5b8088303f15f2b604812a80 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Fri, 18 Oct 2024 21:17:12 +0200
+Subject: [PATCH 05/15] lx2160a: support flexible value for CONFIG_DDR_NODIMM
+
+Add support for values other than 0 and 1 for CONFIG_DDR_NODIMM.
+This macro can be used for both enabling, and selecting a specific
+memory configuration at compile-time.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ plat/nxp/common/plat_make_helper/plat_common_def.mk | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/plat/nxp/common/plat_make_helper/plat_common_def.mk b/plat/nxp/common/plat_make_helper/plat_common_def.mk
+index a1038a073..ed6e0bdac 100644
+--- a/plat/nxp/common/plat_make_helper/plat_common_def.mk
++++ b/plat/nxp/common/plat_make_helper/plat_common_def.mk
+@@ -39,8 +39,9 @@ ifneq (${NUM_OF_DDRC},)
+ $(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
+ endif
+
+-ifeq (${CONFIG_DDR_NODIMM},1)
+-$(eval $(call add_define,CONFIG_DDR_NODIMM))
++CONFIG_DDR_NODIMM ?= 0
++ifneq (${CONFIG_DDR_NODIMM},0)
++$(eval $(call add_define_val,CONFIG_DDR_NODIMM,${CONFIG_DDR_NODIMM}))
+ DDRC_NUM_DIMM := 1
+ endif
+
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0006-plat-nxp-layerscape-mmap-dynamic-configuration-regio.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0006-plat-nxp-layerscape-mmap-dynamic-configuration-regio.patch
new file mode 100644
index 0000000000..4179fcbfae
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0006-plat-nxp-layerscape-mmap-dynamic-configuration-regio.patch
@@ -0,0 +1,48 @@
+From 1dea78ec49250e2c1983fc93ea4c6e3d82196353 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sat, 1 Mar 2025 12:32:03 +0100
+Subject: [PATCH 06/15] plat: nxp: layerscape: mmap dynamic configuration
+ region in bl2
+
+Even before DDR configuration BL2 may wish to modify dynamic
+configuration registers e.g. for changing pinmux and implementing an
+unstucking procedure on i2c bus.
+
+Add mapping for DCFG area in BL2 and increment MAX_MMAP_REGIONS by one.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ plat/nxp/common/include/default/plat_default_def.h | 2 +-
+ plat/nxp/common/setup/ls_common.c | 3 +++
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/plat/nxp/common/include/default/plat_default_def.h b/plat/nxp/common/include/default/plat_default_def.h
+index 7f3298006..5669cbad9 100644
+--- a/plat/nxp/common/include/default/plat_default_def.h
++++ b/plat/nxp/common/include/default/plat_default_def.h
+@@ -147,7 +147,7 @@
+ /* Check if this size can be determined from array size */
+ #if defined(IMAGE_BL2)
+ #ifndef MAX_MMAP_REGIONS
+-#define MAX_MMAP_REGIONS 8
++#define MAX_MMAP_REGIONS 9
+ #endif
+ #ifndef MAX_XLAT_TABLES
+ #define MAX_XLAT_TABLES 6
+diff --git a/plat/nxp/common/setup/ls_common.c b/plat/nxp/common/setup/ls_common.c
+index 28d6b7266..bb9b3f565 100644
+--- a/plat/nxp/common/setup/ls_common.c
++++ b/plat/nxp/common/setup/ls_common.c
+@@ -31,6 +31,9 @@ const mmap_region_t *plat_ls_get_mmap(void);
+ #ifdef IMAGE_BL2
+ const mmap_region_t plat_ls_mmap[] = {
+ LS_MAP_CCSR,
++#ifdef NXP_DCSR_ADDR
++ LS_MAP_DCSR,
++#endif
+ {0}
+ };
+ #endif
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0007-lx2160a-support-flushing-i2c-bus-before-ddr-init.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0007-lx2160a-support-flushing-i2c-bus-before-ddr-init.patch
new file mode 100644
index 0000000000..8e49c5223d
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0007-lx2160a-support-flushing-i2c-bus-before-ddr-init.patch
@@ -0,0 +1,384 @@
+From 12fe019cb30ef1c5e61267b490c5cd7a07e9248b Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Fri, 25 Oct 2024 15:36:57 +0200
+Subject: [PATCH 07/15] lx2160a: support flushing i2c bus before ddr init
+
+The i2c bus can get locked by a slave device holding sda low, when the
+cpu is reset during a transaction.
+Implement workaround according to LX2160A Chip Errata 07/2020 A-010650.
+
+The workaround is inactive by default and must be explicitly enabled
+through a board platform.mk file defining buses and muxes to flush:
+
+LX2160_FLUSH_IIC: 1D array, takes comma separate uint8 indicating
+human-readable i2c bus number,
+e.g: IIC1 & IIC2 = "1, 2".
+
+LX2160_FLUSH_IIC_MUX: 2D array, takes comma-separated 1D array
+initializer expressions with i2c bus number, mux address on the bus and
+a bitmask for channels to flush,
+e.g. IIC1 mux @ 77, channels 1&2 = "{1, 0x77, 0x03}".
+
+This includes a workaround for pinmux corruption separating between
+read-only and write-only memory for the pinmux values.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+Signed-off-by: Ahmad Shtewe <ahmad.shtewe at solid-run.com>
+---
+ plat/nxp/common/setup/common.mk | 1 +
+ plat/nxp/common/setup/include/plat_common.h | 2 +
+ plat/nxp/common/setup/ls_bl2_el3_setup.c | 1 +
+ plat/nxp/common/setup/ls_i2c_init.c | 289 ++++++++++++++++++++
+ plat/nxp/soc-lx2160a/soc.mk | 6 +
+ 5 files changed, 299 insertions(+)
+ create mode 100644 plat/nxp/common/setup/ls_i2c_init.c
+
+diff --git a/plat/nxp/common/setup/common.mk b/plat/nxp/common/setup/common.mk
+index b7e16ae60..6d952a811 100644
+--- a/plat/nxp/common/setup/common.mk
++++ b/plat/nxp/common/setup/common.mk
+@@ -80,6 +80,7 @@ BL2_SOURCES += drivers/io/io_fip.c \
+ plat/nxp/common/setup/ls_image_load.c \
+ plat/nxp/common/setup/ls_io_storage.c \
+ plat/nxp/common/setup/ls_bl2_el3_setup.c \
++ plat/nxp/common/setup/ls_i2c_init.c \
+ plat/nxp/common/setup/${ARCH}/ls_bl2_mem_params_desc.c
+
+ BL31_SOURCES += plat/nxp/common/setup/ls_bl31_setup.c \
+diff --git a/plat/nxp/common/setup/include/plat_common.h b/plat/nxp/common/setup/include/plat_common.h
+index 45832fa68..1c850ebe2 100644
+--- a/plat/nxp/common/setup/include/plat_common.h
++++ b/plat/nxp/common/setup/include/plat_common.h
+@@ -77,6 +77,8 @@ int open_backend(const uintptr_t spec);
+ void ls_bl2_plat_arch_setup(void);
+ void ls_bl2_el3_plat_arch_setup(void);
+
++void bl2_i2c_init(void);
++
+ enum boot_device {
+ BOOT_DEVICE_IFC_NOR,
+ BOOT_DEVICE_IFC_NAND,
+diff --git a/plat/nxp/common/setup/ls_bl2_el3_setup.c b/plat/nxp/common/setup/ls_bl2_el3_setup.c
+index a4cbaef45..63e3460d7 100644
+--- a/plat/nxp/common/setup/ls_bl2_el3_setup.c
++++ b/plat/nxp/common/setup/ls_bl2_el3_setup.c
+@@ -276,6 +276,7 @@ void bl2_el3_plat_prepare_exit(void)
+ */
+ void bl2_plat_preload_setup(void)
+ {
++ bl2_i2c_init();
+
+ soc_preload_setup();
+
+diff --git a/plat/nxp/common/setup/ls_i2c_init.c b/plat/nxp/common/setup/ls_i2c_init.c
+new file mode 100644
+index 000000000..bbb59c476
+--- /dev/null
++++ b/plat/nxp/common/setup/ls_i2c_init.c
+@@ -0,0 +1,289 @@
++#include <stdint.h>
++#include <stdio.h>
++#include <stdlib.h>
++#include <string.h>
++
++#include <common/debug.h>
++#include <drivers/delay_timer.h>
++#include <i2c.h>
++#include <soc.h>
++
++#define NXP_IIC1_ADDR 0x02000000
++#define NXP_IIC2_ADDR 0x02010000
++#define NXP_IIC3_ADDR 0x02020000
++#define NXP_IIC4_ADDR 0x02030000
++#define NXP_IIC5_ADDR 0x02040000
++#define NXP_IIC6_ADDR 0x02050000
++#define NXP_IIC7_ADDR 0x02060000
++#define NXP_IIC8_ADDR 0x02070000
++
++#define RCWSR12R 0x01e0012c
++#define RCWSR12W 0x70010012c
++#define RCWSR12_IIC2_PMUX_MASK 0x00000007 /* [0..2] */
++#define RCWSR12_IIC2_PMUX_IIC2 0x00000000
++#define RCWSR12_IIC2_PMUX_GPIO 0x00000001
++#define RCWSR12_IIC3_PMUX_MASK 0x00000038 /* [3..5] */
++#define RCWSR12_IIC3_PMUX_IIC3 0x00000000
++#define RCWSR12_IIC3_PMUX_GPIO 0x00000008
++#define RCWSR12_IIC4_PMUX_MASK 0x000001c0 /* [6..8] */
++#define RCWSR12_IIC4_PMUX_IIC4 0x00000000
++#define RCWSR12_IIC4_PMUX_GPIO 0x00000040
++#define RCWSR12_IIC5_PMUX_MASK 0x00000e00 /* [9..11] */
++#define RCWSR12_IIC5_PMUX_IIC5 0x00000000
++#define RCWSR12_IIC5_PMUX_GPIO 0x00000200
++#define RCWSR12_IIC6_PMUX_MASK 0x00007000 /* [12..14] */
++#define RCWSR12_IIC6_PMUX_IIC6 0x00000000
++#define RCWSR12_IIC6_PMUX_GPIO 0x00001000
++#define RCWSR13R 0x01e00130
++#define RCWSR13W 0x700100130
++#define RCWSR12_SDHC2_DAT74_PMUX_MASK 0x00000003
++#define RCWSR12_SDHC2_DAT74_PMUX_SDHC2 0x00000000
++#define RCWSR12_SDHC2_DAT74_PMUX_IIC78 0x00000001
++#define RCWSR14R 0x01e00134
++#define RCWSR14W 0x700100134
++#define RCWSR14_IIC1_PMUX_MASK 0x00000400 /* [10] */
++#define RCWSR14_IIC1_PMUX_IIC1 0x00000000
++#define RCWSR14_IIC1_PMUX_GPIO 0x00000400
++
++static void ls_i2c_flush_pca9547(uint8_t busno, const char *busname, uint8_t address, uint8_t channels);
++static void ls_i2c_flush(uint8_t busno, const char *busname);
++
++/**
++ * Flush i2c buses to make slave devices release sda,
++ * in case the system was reset during a transaction.
++ */
++void bl2_i2c_init() {
++ const uint8_t bus_flush_list[] = {CONFIG_LX2160_FLUSH_IIC};
++ /*
++ * List of muxes and channels to flush. Takes 2D array:
++ * {<bus number>, <mux chip address>, <channel bitmask>},
++ */
++ const uint8_t mux_flush_list[][3] = {CONFIG_LX2160_FLUSH_IIC_MUX};
++ const uintptr_t iic_base_addr[] = {
++ NXP_IIC1_ADDR,
++ NXP_IIC2_ADDR,
++ NXP_IIC3_ADDR,
++ NXP_IIC4_ADDR,
++ NXP_IIC5_ADDR,
++ NXP_IIC6_ADDR,
++ };
++ const char *iic_name[] = {
++ "IIC1",
++ "IIC2",
++ "IIC3",
++ "IIC4",
++ "IIC5",
++ "IIC6",
++ };
++ int i;
++ uint8_t busno;
++ uint8_t address;
++ uint8_t channels;
++
++ /* flush i2c buses */
++ for (i = 0; i < ARRAY_SIZE(bus_flush_list); i++) {
++ busno = bus_flush_list[i] - 1;
++ i2c_init(iic_base_addr[busno]);
++ ls_i2c_flush(busno, iic_name[busno]);
++ }
++
++ /* flush muxes channels */
++ for (i = 0; i < ARRAY_SIZE(mux_flush_list); i++) {
++ busno = mux_flush_list[i][0] - 1;
++ address = mux_flush_list[i][1];
++ channels = mux_flush_list[i][2];
++ i2c_init(iic_base_addr[busno]);
++ ls_i2c_flush_pca9547(busno, iic_name[busno], address, channels);
++ }
++}
++
++static void ls_i2c_flush_pca9547(uint8_t busno, const char *busname, uint8_t chip, uint8_t channels) {
++ uint8_t channel, creg = 0;
++ char buffer[64];
++ int ret;
++
++ /* try read configuration register */
++ ret = i2c_read(chip, 0x00, 1, &creg, 1);
++ if(ret != 0) {
++ /* no device responding at address, skip */
++ return;
++ }
++
++ /* after reset configuration register reads 0x08 */
++ if(creg != 0x08) {
++ /* probably not a pca9547, skip */
++ return;
++ }
++
++ /* flush selected channels */
++ for(uint8_t i = 8; i > 0; i--) {
++ if (!(channels & (1 << (i-1))))
++ continue;
++
++ /* select channel i */
++ channel = 0x08 | (i-1);
++ i2c_write(chip, 0x00, 1, &channel, 1);
++
++ /* flush channel */
++ snprintf(buffer, sizeof(buffer), "%s mux@%02x channel %u", busname, chip, i-1);
++ ls_i2c_flush(busno, buffer);
++ }
++}
++
++static struct i2c_bus_info {
++ uintptr_t pinmux_addr_r;
++ uintptr_t pinmux_addr_w;
++ uint32_t pinmux_mask;
++ uint32_t pinmux_sel;
++ uintptr_t gpio_addr;
++ uint8_t gpio_scl;
++ uint8_t gpio_sda;
++} ls_i2c_bus_info[] = {
++ {
++ .pinmux_addr_r = RCWSR14R,
++ .pinmux_addr_w = RCWSR14W,
++ .pinmux_mask = RCWSR14_IIC1_PMUX_MASK,
++ .pinmux_sel = RCWSR14_IIC1_PMUX_GPIO,
++ .gpio_addr = NXP_GPIO1_ADDR,
++ .gpio_scl = 3, /* GPIO1_DAT03 */
++ .gpio_sda = 2, /* GPIO1_DAT02 */
++ },
++ {
++ .pinmux_addr_r = RCWSR12R,
++ .pinmux_addr_w = RCWSR12W,
++ .pinmux_mask = RCWSR12_IIC2_PMUX_MASK,
++ .pinmux_sel = RCWSR12_IIC2_PMUX_GPIO,
++ .gpio_addr = NXP_GPIO1_ADDR,
++ .gpio_scl = 31, /* GPIO1_DAT31 */
++ .gpio_sda = 30, /* GPIO1_DAT30 */
++ },
++ {
++ .pinmux_addr_r = RCWSR12R,
++ .pinmux_addr_w = RCWSR12W,
++ .pinmux_mask = RCWSR12_IIC3_PMUX_MASK,
++ .pinmux_sel = RCWSR12_IIC3_PMUX_GPIO,
++ .gpio_addr = NXP_GPIO1_ADDR,
++ .gpio_scl = 29, /* GPIO1_DAT29 */
++ .gpio_sda = 28, /* GPIO1_DAT28 */
++ },
++ {
++ .pinmux_addr_r = RCWSR12R,
++ .pinmux_addr_w = RCWSR12W,
++ .pinmux_mask = RCWSR12_IIC4_PMUX_MASK,
++ .pinmux_sel = RCWSR12_IIC4_PMUX_GPIO,
++ .gpio_addr = NXP_GPIO1_ADDR,
++ .gpio_scl = 27, /* GPIO1_DAT27 */
++ .gpio_sda = 26, /* GPIO1_DAT26 */
++ },
++ {
++ .pinmux_addr_r = RCWSR12R,
++ .pinmux_addr_w = RCWSR12W,
++ .pinmux_mask = RCWSR12_IIC5_PMUX_MASK,
++ .pinmux_sel = RCWSR12_IIC5_PMUX_GPIO,
++ .gpio_addr = NXP_GPIO1_ADDR,
++ .gpio_scl = 25, /* GPIO1_DAT25 */
++ .gpio_sda = 24, /* GPIO1_DAT24 */
++ },
++ {
++ .pinmux_addr_r = RCWSR12R,
++ .pinmux_addr_w = RCWSR12W,
++ .pinmux_mask = RCWSR12_IIC6_PMUX_MASK,
++ .pinmux_sel = RCWSR12_IIC6_PMUX_GPIO,
++ .gpio_addr = NXP_GPIO1_ADDR,
++ .gpio_scl = 23, /* GPIO1_DAT23 */
++ .gpio_sda = 22, /* GPIO1_DAT22 */
++ },
++ {
++ .pinmux_addr_r = RCWSR13R,
++ .pinmux_addr_w = RCWSR13W,
++ .pinmux_mask = RCWSR12_SDHC2_DAT74_PMUX_MASK,
++ .pinmux_sel = RCWSR12_SDHC2_DAT74_PMUX_IIC78,
++ .gpio_addr = NXP_GPIO2_ADDR,
++ .gpio_scl = 16, /* GPIO2_DAT16 */
++ .gpio_sda = 15, /* GPIO2_DAT15 */
++ },
++ {
++ .pinmux_addr_r = RCWSR13R,
++ .pinmux_addr_w = RCWSR13W,
++ .pinmux_mask = RCWSR12_SDHC2_DAT74_PMUX_MASK,
++ .pinmux_sel = RCWSR12_SDHC2_DAT74_PMUX_IIC78,
++ .gpio_addr = NXP_GPIO2_ADDR,
++ .gpio_scl = 18, /* GPIO2_DAT18 */
++ .gpio_sda = 17, /* GPIO2_DAT17 */
++ },
++};
++
++/*
++ * Flush the i2c bus through any muxes with 9 clock cycles
++ * to ensure all slave devices release their locks on SDA.
++ * This is a work-around for i2c slave devices locking SDA,
++ * when the system has been reset during a transaction.
++ *
++ * The implementation is inspired by LX2160A Chip Errata 07/2020 A-010650.
++ */
++static void ls_i2c_flush(uint8_t busno, const char *busname) {
++ struct i2c_bus_info *info;
++ uintptr_t gpdir_addr, gpodr_addr, gpdat_addr;
++ uint32_t pinmux, gpdir, gpodr, gpdat;
++ struct {
++ uint32_t pinmux, gpdir, gpodr, gpdat;
++ } backup;
++ uint32_t scl_mask, sda_mask;
++
++ if(busno >= 8) {
++ ERROR("failed to flush i2c bus %u %s: invalid bus number!\n", busno, busname);
++ return;
++ }
++ /* load i2c bus specific information */
++ info = &ls_i2c_bus_info[busno];
++ gpdir_addr = info->gpio_addr + 0x0;
++ gpodr_addr = info->gpio_addr + 0x4;
++ gpdat_addr = info->gpio_addr + 0x8;
++ scl_mask = 0x80000000 >> info->gpio_scl;
++ sda_mask = 0x80000000 >> info->gpio_sda;
++
++ /* backup configuration registers */
++ pinmux = backup.pinmux = mmio_read_32(info->pinmux_addr_r);
++ gpdir = backup.gpdir = mmio_read_32(gpdir_addr);
++ gpodr = backup.gpodr = mmio_read_32(gpodr_addr);
++ gpdat = backup.gpdat = mmio_read_32(gpdat_addr);
++
++ /* configure SCL+SDA as GPIOs */
++ pinmux = (pinmux & ~info->pinmux_mask) | info->pinmux_sel;
++ mmio_write_32(info->pinmux_addr_w, pinmux);
++
++ /* configure SCL+SDA as output open drain */
++ gpdir |= scl_mask | sda_mask;
++ gpodr |= scl_mask | sda_mask;
++ gpdat |= scl_mask | sda_mask;
++ mmio_write_32(gpdat_addr, gpdat);
++ mmio_write_32(gpodr_addr, gpodr);
++ mmio_write_32(gpdir_addr, gpdir);
++
++ /* allow short delay for changes to propagate */
++ udelay(10);
++
++ /*
++ * reliable detection of blocked bus is hard
++ * because sda depends on the last sent bit.
++ * Flush unconditionally instead.
++ */
++
++ VERBOSE("flushing i2c bus %u (%s)\n", busno, busname);
++
++ /* toggle clock 9 times */
++ for(uint8_t i = 0; i < 9; i++) {
++ mmio_write_32(gpdat_addr, gpdat & ~scl_mask);
++ udelay(10);
++ mmio_write_32(gpdat_addr, gpdat | scl_mask);
++ udelay(10);
++ }
++
++ /* restore configuration registers */
++ mmio_write_32(gpdir_addr, backup.gpdir);
++ mmio_write_32(gpodr_addr, backup.gpodr);
++ mmio_write_32(gpdat_addr, backup.gpdat);
++ mmio_write_32(info->pinmux_addr_w, backup.pinmux);
++
++ return;
++}
+diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk
+index 20e64753c..fa8c63251 100644
+--- a/plat/nxp/soc-lx2160a/soc.mk
++++ b/plat/nxp/soc-lx2160a/soc.mk
+@@ -185,3 +185,9 @@ ifneq (${LX2160A_S5_GPIO_ADDR},0)
+ $(eval $(call add_define_val,CONFIG_LX2160A_S5_GPIO_ADDR,$(LX2160A_S5_GPIO_ADDR)))
+ $(eval $(call add_define_val,CONFIG_LX2160A_S5_GPIO,$(LX2160A_S5_GPIO)))
+ endif
++
++# I2C Bus Flushing (optional)
++LX2160_FLUSH_IIC ?= ""
++LX2160_FLUSH_IIC_MUX ?= ""
++$(eval $(call add_define_val,CONFIG_LX2160_FLUSH_IIC,"$(LX2160_FLUSH_IIC)"))
++$(eval $(call add_define_val,CONFIG_LX2160_FLUSH_IIC_MUX,"$(LX2160_FLUSH_IIC_MUX)"))
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0008-nxp-ddr-dump-SPD-EEPROM-content-on-debug-builds.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0008-nxp-ddr-dump-SPD-EEPROM-content-on-debug-builds.patch
new file mode 100644
index 0000000000..8ebbd69d88
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0008-nxp-ddr-dump-SPD-EEPROM-content-on-debug-builds.patch
@@ -0,0 +1,40 @@
+From b275d59644e4423427b8cae2890096061d04264c Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Wed, 12 Feb 2025 17:33:41 +0100
+Subject: [PATCH 08/15] nxp: ddr: dump SPD EEPROM content on debug builds
+
+When building with DDR_DEBUG=yes dump the raw SPD EEPROM byte for byte
+on each DIMM.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ drivers/nxp/ddr/nxp-ddr/ddr.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/drivers/nxp/ddr/nxp-ddr/ddr.c b/drivers/nxp/ddr/nxp-ddr/ddr.c
+index 17c2bbb2a..9b788c6c4 100644
+--- a/drivers/nxp/ddr/nxp-ddr/ddr.c
++++ b/drivers/nxp/ddr/nxp-ddr/ddr.c
+@@ -550,6 +550,19 @@ static int parse_spd(struct ddr_info *priv)
+ continue;
+ }
+
++#ifdef DDR_DEBUG
++ /* dump SPD */
++ printf("RAW SPD:");
++ for (size_t k = 0; k < sizeof(struct ddr4_spd); k++) {
++ unsigned char byte = ((unsigned char *)&spd[spd_idx])[k];
++ if (!(k % 16))
++ printf("\n%02x", byte);
++ else
++ printf(" %02x", byte);
++ }
++ printf("\n");
++#endif
++
+ spd_checksum[spd_idx] =
+ (spd[spd_idx].crc[1] << 24) |
+ (spd[spd_idx].crc[0] << 16) |
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0009-nxp-ddr-disarm-error-when-using-non-identical-DIMMs.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0009-nxp-ddr-disarm-error-when-using-non-identical-DIMMs.patch
new file mode 100644
index 0000000000..4cdf0e3dcc
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0009-nxp-ddr-disarm-error-when-using-non-identical-DIMMs.patch
@@ -0,0 +1,35 @@
+From d762fa8d3509be534d0c4b8f07b52e87a1d0a663 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Wed, 12 Feb 2025 17:35:04 +0100
+Subject: [PATCH 09/15] nxp: ddr: disarm error when using non-identical DIMMs
+
+Some DDR4 SO-DIMM report different timings when they are installed in
+different slots. This triggers an error as LX2160A intends to only
+support identical DIMMs.
+
+Disarm the error and continue with timings read from first DIMM SPD.
+An error is printed advising users to carefully check their memory.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ drivers/nxp/ddr/nxp-ddr/ddr.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/nxp/ddr/nxp-ddr/ddr.c b/drivers/nxp/ddr/nxp-ddr/ddr.c
+index 9b788c6c4..0a9cd7f87 100644
+--- a/drivers/nxp/ddr/nxp-ddr/ddr.c
++++ b/drivers/nxp/ddr/nxp-ddr/ddr.c
+@@ -584,8 +584,8 @@ static int parse_spd(struct ddr_info *priv)
+
+ if (spd_idx != 0 && spd_checksum[0] !=
+ spd_checksum[spd_idx]) {
+- ERROR("Not identical DIMMs.\n");
+- return -EINVAL;
++ ERROR("SPD different between DIMMs, using first DIMM timings for all slots.\n");
++ ERROR("Timings might be wrong, replace or carefully validate your memory!\n");
+ }
+ conf->dimm_in_use[j] = 1;
+ valid_mask |= 1 << addr_idx;
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0010-nxp-ddr-add-debug-output-for-dimm-parameters-parsed-.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0010-nxp-ddr-add-debug-output-for-dimm-parameters-parsed-.patch
new file mode 100644
index 0000000000..8d3e7fa3ee
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0010-nxp-ddr-add-debug-output-for-dimm-parameters-parsed-.patch
@@ -0,0 +1,83 @@
+From 54ec59537e12bb9f653b5375803c5f4f03d17060 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Thu, 26 Sep 2024 16:35:40 +0200
+Subject: [PATCH 10/15] nxp: ddr: add debug output for dimm parameters parsed
+ from spd or static
+
+Add debug prints for all members of struct dimm_params, after either
+parsing of SPD - or from static (no-dimm) configuration.
+
+This enables comparison of parameters derived from SPD with static
+configuration.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ drivers/nxp/ddr/nxp-ddr/ddr.c | 52 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 52 insertions(+)
+
+diff --git a/drivers/nxp/ddr/nxp-ddr/ddr.c b/drivers/nxp/ddr/nxp-ddr/ddr.c
+index 0a9cd7f87..b8b28c55a 100644
+--- a/drivers/nxp/ddr/nxp-ddr/ddr.c
++++ b/drivers/nxp/ddr/nxp-ddr/ddr.c
+@@ -629,6 +629,58 @@ static int parse_spd(struct ddr_info *priv)
+ /* now we have valid and identical DIMMs on controllers */
+ #endif /* CONFIG_DDR_NODIMM */
+
++ debug("DIMM: n_ranks = %u\n", dimm->n_ranks);
++ debug("DIMM: die_density = %u\n", dimm->die_density);
++ debug("DIMM: rank_density = %llu\n", dimm->rank_density);
++ debug("DIMM: capacity = %llu\n", dimm->capacity);
++ debug("DIMM: primary_sdram_width = %u\n", dimm->primary_sdram_width);
++ debug("DIMM: ec_sdram_width = %u\n", dimm->ec_sdram_width);
++ debug("DIMM: rdimm = %u\n", dimm->rdimm);
++ debug("DIMM: package_3ds = %u\n", dimm->package_3ds);
++ debug("DIMM: device_width = %u\n", dimm->device_width);
++ debug("DIMM: rc = %u\n", dimm->rc);
++
++ debug("DIMM: n_row_addr = %u\n", dimm->n_row_addr);
++ debug("DIMM: n_col_addr = %u\n", dimm->n_col_addr);
++ debug("DIMM: edc_config = %u\n", dimm->edc_config);
++ debug("DIMM: bank_addr_bits = %u\n", dimm->bank_addr_bits);
++ debug("DIMM: bank_group_bits = %u\n", dimm->bank_group_bits);
++ debug("DIMM: burst_lengths_bitmask = %u\n", dimm->burst_lengths_bitmask);
++
++ debug("DIMM: mirrored_dimm = %u\n", dimm->mirrored_dimm);
++
++ debug("DIMM: mtb_ps = %d\n", dimm->mtb_ps);
++ debug("DIMM: ftb_10th_ps = %d\n", dimm->ftb_10th_ps);
++ debug("DIMM: taa_ps = %d\n", dimm->taa_ps);
++ debug("DIMM: tfaw_ps = %d\n", dimm->tfaw_ps);
++
++ debug("DIMM: tckmin_x_ps = %d\n", dimm->tckmin_x_ps);
++ debug("DIMM: tckmax_ps = %d\n", dimm->tckmax_ps);
++
++ debug("DIMM: caslat_x = %u\n", dimm->caslat_x);
++
++ debug("DIMM: trcd_ps = %d\n", dimm->trcd_ps);
++ debug("DIMM: trp_ps = %d\n", dimm->trp_ps);
++ debug("DIMM: tras_ps = %d\n", dimm->tras_ps);
++
++ debug("DIMM: trfc1_ps = %d\n", dimm->trfc1_ps);
++ debug("DIMM: trfc2_ps = %d\n", dimm->trfc2_ps);
++ debug("DIMM: trfc4_ps = %d\n", dimm->trfc4_ps);
++ debug("DIMM: trrds_ps = %d\n", dimm->trrds_ps);
++ debug("DIMM: trrdl_ps = %d\n", dimm->trrdl_ps);
++ debug("DIMM: tccdl_ps = %d\n", dimm->tccdl_ps);
++ debug("DIMM: trfc_slr_ps = %d\n", dimm->trfc_slr_ps);
++
++ debug("DIMM: trc_ps = %d\n", dimm->trc_ps);
++ debug("DIMM: twr_ps = %d\n", dimm->twr_ps);
++
++ debug("DIMM: refresh_rate_ps = %u\n", dimm->refresh_rate_ps);
++ debug("DIMM: extended_op_srt = %u\n", dimm->extended_op_srt);
++
++ debug("DIMM: rcw = [%u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u]\n", (unsigned int)dimm->rcw[0], (unsigned int)dimm->rcw[1], (unsigned int)dimm->rcw[2], (unsigned int)dimm->rcw[3], (unsigned int)dimm->rcw[4], (unsigned int)dimm->rcw[5], (unsigned int)dimm->rcw[6], (unsigned int)dimm->rcw[7], (unsigned int)dimm->rcw[8], (unsigned int)dimm->rcw[9], (unsigned int)dimm->rcw[10], (unsigned int)dimm->rcw[11], (unsigned int)dimm->rcw[12], (unsigned int)dimm->rcw[13], (unsigned int)dimm->rcw[14], (unsigned int)dimm->rcw[15]);
++ debug("DIMM: dq_mapping = [%u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u]\n", dimm->dq_mapping[0], dimm->dq_mapping[1], dimm->dq_mapping[2], dimm->dq_mapping[3], dimm->dq_mapping[4], dimm->dq_mapping[5], dimm->dq_mapping[6], dimm->dq_mapping[7], dimm->dq_mapping[8], dimm->dq_mapping[9], dimm->dq_mapping[10], dimm->dq_mapping[11], dimm->dq_mapping[12], dimm->dq_mapping[13], dimm->dq_mapping[14], dimm->dq_mapping[15], dimm->dq_mapping[16], dimm->dq_mapping[17]);
++ debug("DIMM: dq_mapping_ors = %u\n", dimm->dq_mapping_ors);
++
+ debug("cal cs\n");
+ conf->cs_in_use = 0;
+ for (j = 0; j < DDRC_NUM_DIMM; j++) {
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0011-plat-lx2160a-fix-building-without-NXP_NV_SW_MAINT_LA.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0011-plat-lx2160a-fix-building-without-NXP_NV_SW_MAINT_LA.patch
new file mode 100644
index 0000000000..717e662351
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0011-plat-lx2160a-fix-building-without-NXP_NV_SW_MAINT_LA.patch
@@ -0,0 +1,49 @@
+From 7d2945375429a4e28b6252c548b8a60114fb791f Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Tue, 30 Jul 2024 17:45:33 +0300
+Subject: [PATCH 11/15] plat: lx2160a: fix building without
+ NXP_NV_SW_MAINT_LAST_EXEC_DATA
+
+Fix compiler errors encountered when disabling non-volatile storage of
+execution state (NXP_NV_SW_MAINT_LAST_EXEC_DATA := no) while keeping
+watchdog restart enabled (NXP_WDOG_RESTART := yes).
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ drivers/nxp/ddr/phy-gen2/phy.h | 2 +-
+ plat/nxp/soc-lx2160a/soc.c | 2 ++
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/nxp/ddr/phy-gen2/phy.h b/drivers/nxp/ddr/phy-gen2/phy.h
+index 5e80f3638..7ddc7c7c6 100644
+--- a/drivers/nxp/ddr/phy-gen2/phy.h
++++ b/drivers/nxp/ddr/phy-gen2/phy.h
+@@ -6,7 +6,7 @@
+ #if !defined(PHY_H) && defined(NXP_WARM_BOOT)
+ #define PHY_H
+
+-#include <flash_info.h>
++#include <drivers/nxp/flexspi/flash_info.h>
+
+ /* To store sector size to be erase on flash*/
+ #define PHY_ERASE_SIZE F_SECTOR_ERASE_SZ
+diff --git a/plat/nxp/soc-lx2160a/soc.c b/plat/nxp/soc-lx2160a/soc.c
+index ca6ae8c93..17556f19d 100644
+--- a/plat/nxp/soc-lx2160a/soc.c
++++ b/plat/nxp/soc-lx2160a/soc.c
+@@ -524,10 +524,12 @@ void soc_init(void)
+ static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags,
+ void *handle, void *cookie)
+ {
++#ifdef NXP_NV_SW_MAINT_LAST_EXEC_DATA
+ uint8_t data = WDOG_RESET_FLAG;
+
+ wr_nv_app_data(WDT_RESET_FLAG_OFFSET,
+ (uint8_t *)&data, sizeof(data));
++#endif
+
+ mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT);
+
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0012-plat-lx2160a-fix-boot-without-spi-flash-disable-non-.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0012-plat-lx2160a-fix-boot-without-spi-flash-disable-non-.patch
new file mode 100644
index 0000000000..d72e2fe8d8
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0012-plat-lx2160a-fix-boot-without-spi-flash-disable-non-.patch
@@ -0,0 +1,33 @@
+From 1b4b3d575f085bdaa078b68a70fc8800a2be4f81 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Tue, 30 Jul 2024 17:45:38 +0300
+Subject: [PATCH 12/15] plat: lx2160a: fix boot without spi flash / disable
+ non-volatile storage
+
+Watchdog restart function does not require book-keeping on non-volatile
+storage.
+Remove explicit enabling of NXP_NV_SW_MAINT_LAST_EXEC_DATA.
+
+This fixed hang during boot where atf gets stuck trying to erase a
+sector of spi flash.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ plat/nxp/soc-lx2160a/soc.mk | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk
+index fa8c63251..4e864e164 100644
+--- a/plat/nxp/soc-lx2160a/soc.mk
++++ b/plat/nxp/soc-lx2160a/soc.mk
+@@ -28,7 +28,6 @@ NXP_WDOG_RESTART := yes
+
+ # for features enabled above.
+ ifeq (${NXP_WDOG_RESTART}, yes)
+-NXP_NV_SW_MAINT_LAST_EXEC_DATA := yes
+ LS_EL3_INTERRUPT_HANDLER := yes
+ $(eval $(call add_define, NXP_WDOG_RESTART))
+ endif
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0013-add-separate-platform-for-solidrun-cex7-module.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0013-add-separate-platform-for-solidrun-cex7-module.patch
new file mode 100644
index 0000000000..be8ddcfeda
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0013-add-separate-platform-for-solidrun-cex7-module.patch
@@ -0,0 +1,423 @@
+From 227479dca0dd27a5dddfd1b35c3fa4442c8bedac Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Fri, 18 Oct 2024 15:11:53 +0200
+Subject: [PATCH 13/15] add separate platform for solidrun cex7 module
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c | 116 ++++++++++++++++++
+ plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h | 105 ++++++++++++++++
+ plat/nxp/soc-lx2160a/lx2160acex7/platform.c | 29 +++++
+ plat/nxp/soc-lx2160a/lx2160acex7/platform.mk | 61 +++++++++
+ .../soc-lx2160a/lx2160acex7/platform_def.h | 14 +++
+ plat/nxp/soc-lx2160a/lx2160acex7/policy.h | 38 ++++++
+ 6 files changed, 363 insertions(+)
+ create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c
+ create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h
+ create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/platform.c
+ create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/platform.mk
+ create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/platform_def.h
+ create mode 100644 plat/nxp/soc-lx2160a/lx2160acex7/policy.h
+
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c b/plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c
+new file mode 100644
+index 000000000..340a20455
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2160acex7/ddr_init.c
+@@ -0,0 +1,116 @@
++/*
++ * Copyright 2021 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#include <assert.h>
++#include <errno.h>
++#include <stdbool.h>
++#include <stdint.h>
++#include <stdio.h>
++#include <stdlib.h>
++#include <string.h>
++
++#include <common/debug.h>
++#include <ddr.h>
++#include <lib/utils.h>
++#include <load_img.h>
++
++#include "plat_common.h"
++#include <platform_def.h>
++
++#if defined(CONFIG_STATIC_DDR) || defined(CONFIG_DDR_NODIMM)
++#error not implemented
++#endif /* defined(CONFIG_STATIC_DDR) || defined(CONFIG_DDR_NODIMM) */
++
++int ddr_board_options(struct ddr_info *priv)
++{
++ struct memctl_opt *popts = &priv->opt;
++ const struct ddr_conf *conf = &priv->conf;
++
++ popts->vref_dimm = U(0x24); /* range 1, 83.4% */
++ popts->rtt_override = 0U;
++ popts->rtt_park = U(240);
++ popts->otf_burst_chop_en = 0;
++ popts->burst_length = U(DDR_BL8);
++ popts->trwt_override = 1U;
++ popts->bstopre = 0U; /* auto precharge */
++ popts->addr_hash = 1;
++
++ /* Set ODT impedance on PHY side */
++ switch (conf->cs_on_dimm[1]) {
++ case 0xc: /* Two slots dual rank */
++ case 0x4: /* Two slots single rank, not valid for interleaving */
++ popts->trwt = U(0xf);
++ popts->twrt = U(0x7);
++ popts->trrt = U(0x7);
++ popts->twwt = U(0x7);
++ popts->vref_phy = U(0x6B); /* 83.6% */
++ popts->odt = U(60);
++ popts->phy_tx_impedance = U(28);
++ break;
++ case 0: /* One slot used */
++ default:
++ popts->trwt = U(0x3);
++ popts->twrt = U(0x3);
++ popts->trrt = U(0x3);
++ popts->twwt = U(0x3);
++ popts->vref_phy = U(0x60); /* 75% */
++ popts->odt = U(48);
++ popts->phy_tx_impedance = U(28);
++ break;
++ }
++
++ return 0;
++}
++
++long long init_ddr(void)
++{
++ int spd_addr[] = { 0x51, 0x52, 0x53, 0x54 };
++ struct ddr_info info;
++ struct sysinfo sys;
++ long long dram_size;
++
++ zeromem(&sys, sizeof(sys));
++ if (get_clocks(&sys) != 0) {
++ ERROR("System clocks are not set\n");
++ panic();
++ }
++ debug("platform clock %lu\n", sys.freq_platform);
++ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
++ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
++
++ zeromem(&info, sizeof(info));
++
++ /* Set two DDRC. Unused DDRC will be removed automatically. */
++ info.num_ctlrs = NUM_OF_DDRC;
++ info.spd_addr = spd_addr;
++ info.ddr[0] = (void *)NXP_DDR_ADDR;
++ info.ddr[1] = (void *)NXP_DDR2_ADDR;
++ info.phy[0] = (void *)NXP_DDR_PHY1_ADDR;
++ info.phy[1] = (void *)NXP_DDR_PHY2_ADDR;
++ info.clk = get_ddr_freq(&sys, 0);
++ info.img_loadr = load_img;
++ info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER;
++ if (info.clk == 0) {
++ info.clk = get_ddr_freq(&sys, 1);
++ }
++ info.dimm_on_ctlr = DDRC_NUM_DIMM;
++
++ info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED;
++
++ dram_size = dram_init(&info
++#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
++ , NXP_CCN_HN_F_0_ADDR
++#endif
++ );
++
++
++ if (dram_size < 0) {
++ ERROR("DDR init failed.\n");
++ }
++
++ return dram_size;
++}
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h b/plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h
+new file mode 100644
+index 000000000..02f51e74d
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2160acex7/plat_def.h
+@@ -0,0 +1,105 @@
++/*
++ * Copyright 2021 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#ifndef PLAT_DEF_H
++#define PLAT_DEF_H
++
++#include <arch.h>
++#include <cortex_a72.h>
++/* Required without TBBR.
++ * To include the defines for DDR PHY
++ * Images.
++ */
++#include <tbbr_img_def.h>
++
++#include <policy.h>
++#include <soc.h>
++
++#if defined(IMAGE_BL31)
++#define LS_SYS_TIMCTL_BASE 0x2890000
++#define PLAT_LS_NSTIMER_FRAME_ID 0
++#define LS_CONFIG_CNTACR 1
++#endif
++
++#define NXP_SYSCLK_FREQ 100000000
++#define NXP_DDRCLK_FREQ 100000000
++
++/* UART related definition */
++#define NXP_CONSOLE_ADDR NXP_UART_ADDR
++#define NXP_CONSOLE_BAUDRATE 115200
++
++/* Size of cacheable stacks */
++#if defined(IMAGE_BL2)
++#if defined(TRUSTED_BOARD_BOOT)
++#define PLATFORM_STACK_SIZE 0x2000
++#else
++#define PLATFORM_STACK_SIZE 0x1000
++#endif
++#elif defined(IMAGE_BL31)
++#define PLATFORM_STACK_SIZE 0x1000
++#endif
++
++/* SD block buffer */
++#define NXP_SD_BLOCK_BUF_SIZE (0x8000)
++#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
++ - NXP_SD_BLOCK_BUF_SIZE)
++
++#ifdef SD_BOOT
++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
++ - NXP_SD_BLOCK_BUF_SIZE)
++#else
++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
++#endif
++
++/* IO defines as needed by IO driver framework */
++#define MAX_IO_DEVICES 4
++#define MAX_IO_BLOCK_DEVICES 1
++#define MAX_IO_HANDLES 4
++
++#define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ)
++
++/*
++ * FIP image defines - Offset at which FIP Image would be present
++ * Image would include Bl31 , Bl33 and Bl32 (optional)
++ */
++#ifdef POLICY_FUSE_PROVISION
++#define MAX_FIP_DEVICES 3
++#endif
++
++#ifndef MAX_FIP_DEVICES
++#define MAX_FIP_DEVICES 2
++#endif
++
++/*
++ * ID of the secure physical generic timer interrupt used by the BL32.
++ */
++#define BL32_IRQ_SEC_PHY_TIMER 29
++
++#define BL31_WDOG_SEC 89
++
++#define BL31_NS_WDOG_WS1 108
++
++/*
++ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
++ * terminology. On a GICv2 system or mode, the lists will be merged and treated
++ * as Group 0 interrupts.
++ */
++#define PLAT_LS_G1S_IRQ_PROPS(grp) \
++ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
++ GIC_INTR_CFG_EDGE)
++
++/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
++#define NXP_IRQ_SEC_SGI_7 15
++
++#define PLAT_LS_G0_IRQ_PROPS(grp) \
++ INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
++ GIC_INTR_CFG_EDGE), \
++ INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \
++ GIC_INTR_CFG_EDGE), \
++ INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
++ GIC_INTR_CFG_LEVEL)
++#endif
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/platform.c b/plat/nxp/soc-lx2160a/lx2160acex7/platform.c
+new file mode 100644
+index 000000000..b00adb51d
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2160acex7/platform.c
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2021 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#include <plat_common.h>
++
++#pragma weak board_enable_povdd
++#pragma weak board_disable_povdd
++
++bool board_enable_povdd(void)
++{
++#ifdef CONFIG_POVDD_ENABLE
++ return true;
++#else
++ return false;
++#endif
++}
++
++bool board_disable_povdd(void)
++{
++#ifdef CONFIG_POVDD_ENABLE
++ return true;
++#else
++ return false;
++#endif
++}
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk b/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk
+new file mode 100644
+index 000000000..0b064bbbf
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2160acex7/platform.mk
+@@ -0,0 +1,61 @@
++#
++# Copyright 2021 NXP
++#
++# SPDX-License-Identifier: BSD-3-Clause
++#
++
++# board-specific build parameters
++
++BOOT_MODE ?= flexspi_nor
++BOARD ?= lx2160acex7
++POVDD_ENABLE := no
++NXP_COINED_BB := no
++
++ # DDR Compilation Configs
++NUM_OF_DDRC := 2
++DDRC_NUM_DIMM := 2
++DDRC_NUM_CS := 4
++DDR_ECC_EN := yes
++ #enable address decoding feature
++DDR_ADDR_DEC := yes
++APPLY_MAX_CDD := yes
++
++# S5 GPIO
++LX2160A_S5_GPIO_ADDR := NXP_GPIO3_ADDR
++LX2160A_S5_GPIO := 7
++
++# I2C Bus Flushing: IIC1
++LX2160_FLUSH_IIC := 1,
++# I2C Mux Flushing: IIC1: PCA9547 at 77: Channel 0 (SPD EEPROM)
++LX2160_FLUSH_IIC_MUX := { 1, 0x77, 0x01 },
++
++# DDR Errata
++ERRATA_DDR_A011396 := 1
++ERRATA_DDR_A050450 := 1
++
++ # On-Board Flash Details
++FLASH_TYPE := MT35XU512A
++XSPI_FLASH_SZ := 0x10000000
++NXP_XSPI_NOR_UNIT_SIZE := 0x20000
++BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000
++# CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This
++# config is enabled for future use cases.
++FSPI_ERASE_4K := 0
++
++ # Platform specific features.
++WARM_BOOT := no
++
++ # Adding Platform files build files
++BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
++ ${BOARD_PATH}/platform.c
++
++SUPPORTED_BOOT_MODE := flexspi_nor \
++ sd \
++ emmc \
++ auto
++
++# Adding platform board build info
++include plat/nxp/common/plat_make_helper/plat_common_def.mk
++
++ # Adding SoC build info
++include plat/nxp/soc-lx2160a/soc.mk
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/platform_def.h b/plat/nxp/soc-lx2160a/lx2160acex7/platform_def.h
+new file mode 100644
+index 000000000..666099800
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2160acex7/platform_def.h
+@@ -0,0 +1,14 @@
++/*
++ * Copyright 2021 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#ifndef PLATFORM_DEF_H
++#define PLATFORM_DEF_H
++
++#include "plat_def.h"
++#include "plat_default_def.h"
++
++#endif
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex7/policy.h b/plat/nxp/soc-lx2160a/lx2160acex7/policy.h
+new file mode 100644
+index 000000000..19ad6dbec
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2160acex7/policy.h
+@@ -0,0 +1,38 @@
++/*
++ * Copyright 2021 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#ifndef POLICY_H
++#define POLICY_H
++
++/* Following defines affect the PLATFORM SECURITY POLICY */
++
++/* set this to 0x0 if the platform is not using/responding to ECC errors
++ * set this to 0x1 if ECC is being used (we have to do some init)
++ */
++#define POLICY_USING_ECC 0x0
++
++/* Set this to 0x0 to leave the default SMMU page size in sACR
++ * Set this to 0x1 to change the SMMU page size to 64K
++ */
++#define POLICY_SMMU_PAGESZ_64K 0x1
++
++/*
++ * POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I
++ * POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7
++ * POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23
++ */
++#define POLICY_PERF_WRIOP 0
++
++/*
++ * set this to '1' if the debug clocks need to remain enabled during
++ * system entry to low-power (LPM20) - this should only be necessary
++ * for testing and NEVER set for normal production
++ */
++#define POLICY_DEBUG_ENABLE 0
++
++
++#endif /* POLICY_H */
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0014-add-separate-platform-for-solidrun-lx2162a-som.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0014-add-separate-platform-for-solidrun-lx2162a-som.patch
new file mode 100644
index 0000000000..54ebc06412
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0014-add-separate-platform-for-solidrun-lx2162a-som.patch
@@ -0,0 +1,597 @@
+From af19692dce0516d3713353c4de5e9c87ef81d28a Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sun, 27 Oct 2024 18:00:11 +0100
+Subject: [PATCH 14/15] add separate platform for solidrun lx2162a som
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c | 290 ++++++++++++++++++
+ plat/nxp/soc-lx2160a/lx2162asom/plat_def.h | 105 +++++++
+ plat/nxp/soc-lx2160a/lx2162asom/platform.c | 29 ++
+ plat/nxp/soc-lx2160a/lx2162asom/platform.mk | 61 ++++
+ .../nxp/soc-lx2160a/lx2162asom/platform_def.h | 14 +
+ plat/nxp/soc-lx2160a/lx2162asom/policy.h | 38 +++
+ 6 files changed, 537 insertions(+)
+ create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c
+ create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/plat_def.h
+ create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/platform.c
+ create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/platform.mk
+ create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/platform_def.h
+ create mode 100644 plat/nxp/soc-lx2160a/lx2162asom/policy.h
+
+diff --git a/plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c b/plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c
+new file mode 100644
+index 000000000..917acceb2
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2162asom/ddr_init.c
+@@ -0,0 +1,290 @@
++/*
++ * Copyright 2018-2021 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#include <assert.h>
++#include <errno.h>
++#include <stdbool.h>
++#include <stdint.h>
++#include <stdio.h>
++#include <stdlib.h>
++#include <string.h>
++
++#include <common/debug.h>
++#include <ddr.h>
++#include <lib/utils.h>
++#include <load_img.h>
++
++#include "plat_common.h"
++#include <platform_def.h>
++
++#ifdef CONFIG_STATIC_DDR
++#error not implemented
++#elif defined(CONFIG_DDR_NODIMM)
++#if CONFIG_DDR_NODIMM == 1
++/*
++ * SoM Revision 1.1: 9 x K4A8G085WC-BCWE (SDP, 8GB w/ ECC)
++ *
++ * Use in production for units with empty SPD,
++ * and development.
++ */
++static const struct dimm_params static_dimm = {
++ .mpart = "Fixed DDR Config 1",
++ .n_ranks = 1,
++ .die_density = 0x5, // encoded per spd byte 4, 0b101 = 8Gbit
++ .rank_density = 0x200000000, // 8GB
++ .capacity = 0x200000000, // 8GB
++ .primary_sdram_width = 64,
++ .ec_sdram_width = 8, // 8 bit ecc extension
++ .rdimm = 0,
++ .package_3ds = 0,
++ .device_width = 8, // 8 bit per sdram
++ .rc = 0,
++
++ .n_row_addr = 16,
++ .n_col_addr = 10,
++ .edc_config = 2, // enable ecc
++ .bank_addr_bits = 0, // 4 banks
++ .bank_group_bits = 2, // 4 bank groups
++ .burst_lengths_bitmask = 0xc, // enable 4 & 8-bit burst (DDR4 spec)
++
++ .mirrored_dimm = 0,
++
++ // timings based on K4A8G085WC-BCTD (DDR4-2666), missing values for 3200
++ .mtb_ps = 125, // MTB per SPD spec
++ .ftb_10th_ps = 10, // default value, unused by nxp ddr driver
++ .taa_ps = 13750, // min. 13.75ns
++ .tfaw_ps = 21000, // min: max(21ns or 20CK) (this 8Gbit sdram has 1KB pages)
++
++ .tckmin_x_ps = 625, // 3200 (CK=1600)
++ .tckmax_ps = 1250, // 1600 (CK=800)
++
++ .caslat_x = 0b00000001011111111111110000000000, // CL = [10-22,24] (1 << CL)
++
++ .trcd_ps = 13750, // 13.75ns - CL22-22-22
++ .trp_ps = 13750, // 13.75ns - CL22-22-22
++ .tras_ps = 32000, // 32ns
++
++ .trfc1_ps = 350000, // 350ns
++ .trfc2_ps = 260000, // 260ns
++ .trfc4_ps = 160000, // 160ns
++ .trrds_ps = 3300, // min: max(4CK or 3.3ns)
++ .trrdl_ps = 4900, // min: max(4CK or 6.4ns)
++ .tccdl_ps = 5000, // min: max(5CK or 5ns)
++ .trfc_slr_ps = 0,
++
++ .trc_ps = 45750, // tras + trp 45.75ns
++ .twr_ps = 15000, // 15ns
++
++ .refresh_rate_ps = 7800000, // 1x mode 7.8us for standard temperature range (TODO: pick correct range based on temperature?!)
++ // .extended_op_srt = 0,
++
++ // .rcw = {}, // only for registered dimm
++ .dq_mapping = {
++ 0x16, // DQ[0:3]: lower nibble, bit order 3120
++ 0x22, // DQ[4:7]: upper nibble, bit order 4576
++ 0x0e, // DQ[8:11]: lower nibble, bit order 2031
++ 0x30, // DQ[12:15]: upper nibble, bit order 6574
++ 0x14, // DQ[16:19]: lower nibble, bit order 3021
++ 0x36, // DQ[20:23]: upper nibble, bit order 7564
++ 0x11, // DQ[24:27]: lower nibble, bit order 2301
++ 0x2f, // DQ[28:31]: upper nibble, bit order 6547
++ 0x03, // ECC[0:3]: lower nibble, bit order 0213
++ 0x22, // ECC[4:7]: upper nibble, bit order 4576
++ 0x10, // DQ[32:35]: lower nibble, bit order 2130
++ 0x30, // DQ[36:39]: upper nibble, bit order 6574
++ 0x0e, // DQ[40:43]: lower nibble, bit order 2031
++ 0x34, // DQ[44:47]: upper nibble, bit order 7465
++ 0x14, // DQ[48:51]: lower nibble, bit order 3021
++ 0x36, // DQ[52:55]: upper nibble, bit order 7564
++ 0x10, // DQ[56:59]: lower nibble, bit order 2130
++ 0x2b, // DQ[60:63]: upper nibble, bit order 5746
++ },
++ .dq_mapping_ors = 1,
++};
++#endif /* CONFIG_DDR_NODIMM == 1 */
++
++#if CONFIG_DDR_NODIMM == 2
++/*
++ * SoM Revision 1.1: 9 x K4AAG085WA-BCWE (DDP, 16GB w/ ECC)
++ *
++ * Use in production for units with empty SPD,
++ * and development.
++ */
++static const struct dimm_params static_dimm = {
++ .mpart = "Fixed DDR Config 2",
++ .n_ranks = 1,
++ .die_density = 0x6, // encoded per spd byte 4, 0b110 = 16Gbit
++ // TODO: for DDP memory should have 2 ranks per DIMM + correct density per die?
++ .rank_density = 0x400000000, // 16GB
++ .capacity = 0x400000000, // 16GB
++ .primary_sdram_width = 64,
++ .ec_sdram_width = 8, // 8 bit ecc extension
++ .rdimm = 0,
++ .package_3ds = 0,
++ .device_width = 8, // 8 bit per sdram
++ .rc = 0,
++
++ .n_row_addr = 17,
++ .n_col_addr = 10,
++ .edc_config = 2, // enable ecc
++ .bank_addr_bits = 0, // 4 banks
++ .bank_group_bits = 2, // 4 bank groups
++ .burst_lengths_bitmask = 0xc, // enable 4 & 8-bit burst (DDR4 spec)
++
++ .mirrored_dimm = 0,
++
++ .mtb_ps = 125, // MTB per SPD spec
++ .ftb_10th_ps = 10, // default value, unused by nxp ddr driver
++ .taa_ps = 13750, // min. 13.75ns
++ .tfaw_ps = 30000, // min: max(30ns or 28CK) (this 16Gbit sdram has 2KB pages)
++
++ .tckmin_x_ps = 625, // 3200 (CK=1600)
++ .tckmax_ps = 1250, // 1600 (CK=800)
++
++ .caslat_x = 0b00000001011111111111110000000000, // CL = [10-22,24] (1 << CL)
++
++ .trcd_ps = 13750, // 13.75ns
++ .trp_ps = 13750, // 13.75ns
++ .tras_ps = 32000, // 32ns
++
++ .trfc1_ps = 350000, // 350ns, assumed same as 8Gbit SDP module
++ .trfc2_ps = 260000, // 260ns, assumed same as 8Gbit SDP module
++ .trfc4_ps = 160000, // 160ns, assumed same as 8Gbit SDP module
++ .trrds_ps = 5300, // min: max(4CK or 5.3ns)
++ .trrdl_ps = 6400, // min: max(4CK or 6.4ns)
++ .tccdl_ps = 5000, // min: max(5CK or 5ns)
++ .trfc_slr_ps = 0,
++
++ .trc_ps = 45750, // tras + trp 45.75ns
++ .twr_ps = 15000, // 15ns
++
++ .refresh_rate_ps = 7800000, // 1x mode 7.8us for standard temperature range (TODO: pick correct range based on temperature?!)
++ // .extended_op_srt = 0,
++
++ // .rcw = {}, // only for registered dimm
++ .dq_mapping = {
++ 0x16, // DQ[0:3]: lower nibble, bit order 3120
++ 0x22, // DQ[4:7]: upper nibble, bit order 4576
++ 0x0e, // DQ[8:11]: lower nibble, bit order 2031
++ 0x30, // DQ[12:15]: upper nibble, bit order 6574
++ 0x14, // DQ[16:19]: lower nibble, bit order 3021
++ 0x36, // DQ[20:23]: upper nibble, bit order 7564
++ 0x11, // DQ[24:27]: lower nibble, bit order 2301
++ 0x2f, // DQ[28:31]: upper nibble, bit order 6547
++ 0x03, // ECC[0:3]: lower nibble, bit order 0213
++ 0x22, // ECC[4:7]: upper nibble, bit order 4576
++ 0x10, // DQ[32:35]: lower nibble, bit order 2130
++ 0x30, // DQ[36:39]: upper nibble, bit order 6574
++ 0x0e, // DQ[40:43]: lower nibble, bit order 2031
++ 0x34, // DQ[44:47]: upper nibble, bit order 7465
++ 0x14, // DQ[48:51]: lower nibble, bit order 3021
++ 0x36, // DQ[52:55]: upper nibble, bit order 7564
++ 0x10, // DQ[56:59]: lower nibble, bit order 2130
++ 0x2b, // DQ[60:63]: upper nibble, bit order 5746
++ },
++ .dq_mapping_ors = 1,
++};
++#endif /* CONFIG_DDR_NODIMM == 2 */
++
++int ddr_get_ddr_params(struct dimm_params *pdimm,
++ struct ddr_conf *conf)
++{
++ // channel 1
++ conf->dimm_in_use[0] = 1;
++ memcpy(&pdimm[0], &static_dimm, sizeof(struct dimm_params));
++
++ /* 1 module */
++ return 0x1;
++}
++#endif /* defined(CONFIG_DDR_NODIMM) */
++
++int ddr_board_options(struct ddr_info *priv)
++{
++ struct memctl_opt *popts = &priv->opt;
++
++ popts->caslat_override = 0;
++ popts->caslat_override_value = 0;
++ popts->auto_self_refresh_en = 1;
++ popts->output_driver_impedance = 0; // 34 Ohm
++ popts->twot_en = 0;
++ popts->threet_en = 0;
++ popts->addt_lat_override = 0;
++ popts->addt_lat_override_value = 0;
++ popts->phy_atx_impedance = 30;
++ popts->skip2d = 0;
++ popts->vref_dimm = U(0x19); /* range 1, 83.4% */
++
++ popts->rtt_override = 0U;
++ popts->rtt_park = 120U;
++ popts->otf_burst_chop_en = 0;
++ popts->burst_length = DDR_BL8;
++ popts->trwt_override = 1U;
++ popts->bstopre = 0U; /* auto precharge */
++ popts->addr_hash = 1;
++ popts->trwt = U(0x3);
++ popts->twrt = U(0x3);
++ popts->trrt = U(0x3);
++ popts->twwt = U(0x3);
++ popts->vref_phy = U(0x5D); /* 72% */
++ popts->odt = 60U;
++ popts->phy_tx_impedance = 28U;
++
++ return 0;
++}
++
++#ifdef NXP_WARM_BOOT
++long long init_ddr(uint32_t wrm_bt_flg)
++#else
++long long init_ddr(void)
++#endif
++{
++ int spd_addr[] = { 0x51 };
++ struct ddr_info info;
++ struct sysinfo sys;
++ long long dram_size;
++
++ zeromem(&sys, sizeof(sys));
++ if (get_clocks(&sys) != 0) {
++ ERROR("System clocks are not set\n");
++ panic();
++ }
++ debug("platform clock %lu\n", sys.freq_platform);
++ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
++ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
++
++ zeromem(&info, sizeof(info));
++
++ /* Set two DDRC. Unused DDRC will be removed automatically. */
++ info.num_ctlrs = NUM_OF_DDRC;
++ info.spd_addr = spd_addr;
++ info.ddr[0] = (void *)NXP_DDR_ADDR;
++ info.ddr[1] = (void *)NXP_DDR2_ADDR;
++ info.phy[0] = (void *)NXP_DDR_PHY1_ADDR;
++ info.phy[1] = (void *)NXP_DDR_PHY2_ADDR;
++ info.clk = get_ddr_freq(&sys, 0);
++ info.img_loadr = load_img;
++ info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER;
++ if (info.clk == 0) {
++ info.clk = get_ddr_freq(&sys, 1);
++ }
++ info.dimm_on_ctlr = DDRC_NUM_DIMM;
++
++ info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED;
++
++ dram_size = dram_init(&info
++#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
++ , NXP_CCN_HN_F_0_ADDR
++#endif
++ );
++
++
++ if (dram_size < 0) {
++ ERROR("DDR init failed.\n");
++ }
++
++ return dram_size;
++}
+diff --git a/plat/nxp/soc-lx2160a/lx2162asom/plat_def.h b/plat/nxp/soc-lx2160a/lx2162asom/plat_def.h
+new file mode 100644
+index 000000000..de2d2444a
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2162asom/plat_def.h
+@@ -0,0 +1,105 @@
++/*
++ * Copyright 2018-2021 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#ifndef PLAT_DEF_H
++#define PLAT_DEF_H
++
++#include <arch.h>
++#include <cortex_a72.h>
++/* Required without TBBR.
++ * To include the defines for DDR PHY
++ * Images.
++ */
++#include <tbbr_img_def.h>
++
++#include <policy.h>
++#include <soc.h>
++
++#if defined(IMAGE_BL31)
++#define LS_SYS_TIMCTL_BASE 0x2890000
++#define PLAT_LS_NSTIMER_FRAME_ID 0
++#define LS_CONFIG_CNTACR 1
++#endif
++
++#define NXP_SYSCLK_FREQ 100000000
++#define NXP_DDRCLK_FREQ 100000000
++
++/* UART related definition */
++#define NXP_CONSOLE_ADDR NXP_UART_ADDR
++#define NXP_CONSOLE_BAUDRATE 115200
++
++/* Size of cacheable stacks */
++#if defined(IMAGE_BL2)
++#if defined(TRUSTED_BOARD_BOOT)
++#define PLATFORM_STACK_SIZE 0x2000
++#else
++#define PLATFORM_STACK_SIZE 0x1000
++#endif
++#elif defined(IMAGE_BL31)
++#define PLATFORM_STACK_SIZE 0x1000
++#endif
++
++/* SD block buffer */
++#define NXP_SD_BLOCK_BUF_SIZE (0x8000)
++#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
++ - NXP_SD_BLOCK_BUF_SIZE)
++
++#ifdef SD_BOOT
++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
++ - NXP_SD_BLOCK_BUF_SIZE)
++#else
++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
++#endif
++
++/* IO defines as needed by IO driver framework */
++#define MAX_IO_DEVICES 4
++#define MAX_IO_BLOCK_DEVICES 1
++#define MAX_IO_HANDLES 4
++
++#define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ)
++
++/*
++ * FIP image defines - Offset at which FIP Image would be present
++ * Image would include Bl31 , Bl33 and Bl32 (optional)
++ */
++#ifdef POLICY_FUSE_PROVISION
++#define MAX_FIP_DEVICES 3
++#endif
++
++#ifndef MAX_FIP_DEVICES
++#define MAX_FIP_DEVICES 2
++#endif
++
++/*
++ * ID of the secure physical generic timer interrupt used by the BL32.
++ */
++#define BL32_IRQ_SEC_PHY_TIMER 29
++
++#define BL31_WDOG_SEC 89
++
++#define BL31_NS_WDOG_WS1 108
++
++/*
++ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
++ * terminology. On a GICv2 system or mode, the lists will be merged and treated
++ * as Group 0 interrupts.
++ */
++#define PLAT_LS_G1S_IRQ_PROPS(grp) \
++ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
++ GIC_INTR_CFG_EDGE)
++
++/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
++#define NXP_IRQ_SEC_SGI_7 15
++
++#define PLAT_LS_G0_IRQ_PROPS(grp) \
++ INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
++ GIC_INTR_CFG_EDGE), \
++ INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \
++ GIC_INTR_CFG_EDGE), \
++ INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
++ GIC_INTR_CFG_LEVEL)
++#endif
+diff --git a/plat/nxp/soc-lx2160a/lx2162asom/platform.c b/plat/nxp/soc-lx2160a/lx2162asom/platform.c
+new file mode 100644
+index 000000000..7622cf09a
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2162asom/platform.c
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2020 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#include <plat_common.h>
++
++#pragma weak board_enable_povdd
++#pragma weak board_disable_povdd
++
++bool board_enable_povdd(void)
++{
++#ifdef CONFIG_POVDD_ENABLE
++ return true;
++#else
++ return false;
++#endif
++}
++
++bool board_disable_povdd(void)
++{
++#ifdef CONFIG_POVDD_ENABLE
++ return true;
++#else
++ return false;
++#endif
++}
+diff --git a/plat/nxp/soc-lx2160a/lx2162asom/platform.mk b/plat/nxp/soc-lx2160a/lx2162asom/platform.mk
+new file mode 100644
+index 000000000..c1ba077e9
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2162asom/platform.mk
+@@ -0,0 +1,61 @@
++#
++# Copyright 2018-2020 NXP
++#
++# SPDX-License-Identifier: BSD-3-Clause
++#
++
++# board-specific build parameters
++
++BOOT_MODE ?= flexspi_nor
++BOARD ?= lx2162asom
++POVDD_ENABLE := no
++NXP_COINED_BB := no
++
++ # DDR Compilation Configs
++NUM_OF_DDRC := 1
++DDRC_NUM_DIMM := 1
++DDRC_NUM_CS := 2
++DDR_ECC_EN := yes
++ #enable address decoding feature
++DDR_ADDR_DEC := yes
++APPLY_MAX_CDD := yes
++
++# Mock SPD:
++# - 0: disable mock spd
++# - 1: 9 x K4A8G085WC-BCWE SoM v1.1 8GB w/ ECC
++# - 2: 9 x K4AAG085WA-BCWE SoM v1.1 16GB w/ ECC
++CONFIG_DDR_NODIMM := 0
++
++# I2C Bus Flushing: IIC1 (SPD EEPROM)
++LX2160_FLUSH_IIC := 1,
++
++# DDR Errata
++ERRATA_DDR_A011396 := 1
++ERRATA_DDR_A050450 := 1
++
++# On-Board Flash Details
++FLASH_TYPE := MT35XU512A
++XSPI_FLASH_SZ := 0x10000000
++NXP_XSPI_NOR_UNIT_SIZE := 0x20000
++BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000
++# CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This
++# config is enabled for future use cases.
++FSPI_ERASE_4K := 0
++
++# Platform specific features.
++WARM_BOOT := no
++
++# Adding Platform files build files
++BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
++ ${BOARD_PATH}/platform.c
++
++SUPPORTED_BOOT_MODE := flexspi_nor \
++ sd \
++ emmc \
++ auto
++
++# Adding platform board build info
++include plat/nxp/common/plat_make_helper/plat_common_def.mk
++
++# Adding SoC build info
++include plat/nxp/soc-lx2160a/soc.mk
+diff --git a/plat/nxp/soc-lx2160a/lx2162asom/platform_def.h b/plat/nxp/soc-lx2160a/lx2162asom/platform_def.h
+new file mode 100644
+index 000000000..5fa774e90
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2162asom/platform_def.h
+@@ -0,0 +1,14 @@
++/*
++ * Copyright 2018-2020 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#ifndef PLATFORM_DEF_H
++#define PLATFORM_DEF_H
++
++#include "plat_def.h"
++#include "plat_default_def.h"
++
++#endif
+diff --git a/plat/nxp/soc-lx2160a/lx2162asom/policy.h b/plat/nxp/soc-lx2160a/lx2162asom/policy.h
+new file mode 100644
+index 000000000..1095f3840
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2162asom/policy.h
+@@ -0,0 +1,38 @@
++/*
++ * Copyright 2018-2020 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#ifndef POLICY_H
++#define POLICY_H
++
++/* Following defines affect the PLATFORM SECURITY POLICY */
++
++/* set this to 0x0 if the platform is not using/responding to ECC errors
++ * set this to 0x1 if ECC is being used (we have to do some init)
++ */
++#define POLICY_USING_ECC 0x0
++
++/* Set this to 0x0 to leave the default SMMU page size in sACR
++ * Set this to 0x1 to change the SMMU page size to 64K
++ */
++#define POLICY_SMMU_PAGESZ_64K 0x1
++
++/*
++ * POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I
++ * POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7
++ * POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23
++ */
++#define POLICY_PERF_WRIOP 0
++
++/*
++ * set this to '1' if the debug clocks need to remain enabled during
++ * system entry to low-power (LPM20) - this should only be necessary
++ * for testing and NEVER set for normal production
++ */
++#define POLICY_DEBUG_ENABLE 0
++
++
++#endif /* POLICY_H */
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0015-add-separate-platform-for-solidrun-internal-cex6-eva.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0015-add-separate-platform-for-solidrun-internal-cex6-eva.patch
new file mode 100644
index 0000000000..884742de3d
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0015-add-separate-platform-for-solidrun-internal-cex6-eva.patch
@@ -0,0 +1,562 @@
+From c01d1adda6250f35616816913d38b62fc888d9de Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Fri, 18 Oct 2024 15:05:13 +0200
+Subject: [PATCH 15/15] add separate platform for solidrun internal cex6
+ evaluation board
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c | 248 ++++++++++++++++++
+ plat/nxp/soc-lx2160a/lx2160acex6/plat_def.h | 105 ++++++++
+ plat/nxp/soc-lx2160a/lx2160acex6/platform.c | 29 ++
+ plat/nxp/soc-lx2160a/lx2160acex6/platform.mk | 67 +++++
+ .../soc-lx2160a/lx2160acex6/platform_def.h | 14 +
+ plat/nxp/soc-lx2160a/lx2160acex6/policy.h | 38 +++
+ 6 files changed, 501 insertions(+)
+ create mode 100644 plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c
+ create mode 100644 plat/nxp/soc-lx2160a/lx2160acex6/plat_def.h
+ create mode 100644 plat/nxp/soc-lx2160a/lx2160acex6/platform.c
+ create mode 100644 plat/nxp/soc-lx2160a/lx2160acex6/platform.mk
+ create mode 100644 plat/nxp/soc-lx2160a/lx2160acex6/platform_def.h
+ create mode 100644 plat/nxp/soc-lx2160a/lx2160acex6/policy.h
+
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c b/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c
+new file mode 100644
+index 000000000..6e2d3fc6c
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c
+@@ -0,0 +1,248 @@
++/*
++ * Copyright 2021 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#include <assert.h>
++#include <errno.h>
++#include <stdbool.h>
++#include <stdint.h>
++#include <stdio.h>
++#include <stdlib.h>
++#include <string.h>
++
++#include <common/debug.h>
++#include <ddr.h>
++#include <lib/utils.h>
++#include <load_img.h>
++
++#include "plat_common.h"
++#include <platform_def.h>
++
++#ifdef CONFIG_STATIC_DDR
++#error not implemented
++#elif defined(CONFIG_DDR_NODIMM)
++#if CONFIG_DDR_NODIMM == 1
++/*
++ * PCB Revision 1.0: 9 x K4A8G085WC-BCWE TODO
++ */
++#error Not implemented.
++#endif /* CONFIG_DDR_NODIMM == 1 */
++
++#if CONFIG_DDR_NODIMM == 2 || CONFIG_DDR_NODIMM == 3
++/*
++ * PCB Revision 1.1/1.2: 2 x 5 x MT40A1G16TB-062E IT:F
++ */
++#define CONFIG_DDR_NODIMM_CH2
++
++#if CONFIG_DDR_NODIMM == 3
++/* PCB Revision 1.2 supports ECC */
++#define CONFIG_DDR_NODIMM_ECC
++#endif /* CONFIG_DDR_NODIMM == 3 */
++
++static const struct dimm_params static_dimm = {
++ .mpart = "Fixed DDR Config " __XSTRING(CONFIG_DDR_NODIMM),
++ .n_ranks = 1,
++ .die_density = 0x6, // encoded per spd byte 4, 0b110 = 16Gbit
++ .rank_density = 0x200000000, // 16Gbit
++ .capacity = 0x200000000, // 16Gbit
++ .primary_sdram_width = 64,
++#ifdef CONFIG_DDR_NODIMM_ECC
++ .ec_sdram_width = 8, // 8 bit ecc extension
++#else
++ .ec_sdram_width = 0, // no ecc extension
++#endif
++ .rdimm = 0,
++ .package_3ds = 0,
++ .device_width = 16, // 16 bit per sdram
++ .rc = 0,
++
++ .n_row_addr = 17,
++ .n_col_addr = 10,
++#ifdef CONFIG_DDR_NODIMM_ECC
++ .edc_config = 2, // enable ecc
++#else
++ .edc_config = 0, // disable ecc
++#endif
++ .bank_addr_bits = 0, // 4 banks
++ .bank_group_bits = 1, // 2 bank groups
++ .burst_lengths_bitmask = 0xc, // enable 4 & 8-bit burst (DDR4 spec)
++
++ .mirrored_dimm = 0,
++
++ // timings based on MT40A4G4 / MT40A2G8 / MT40A1G16 datasheet (DDR4-3200 22-22-22)
++ .mtb_ps = 125, // MTB per SPD spec
++ .ftb_10th_ps = 10, // default value, unused by nxp ddr driver
++ .taa_ps = 13750, // min. 13.75ns
++ .tfaw_ps = 30000, // min: max(30ns or 28CK) (this 8Gbit sdram has 2KB pages)
++
++ .tckmin_x_ps = 625, // 2400 (CK=1600)
++ .tckmax_ps = 1250, // 1600 (CK=800)
++
++ .caslat_x = 0b00000001011111111111110000000000, // CL = [10-22,24] (1 << CL)
++
++ .trcd_ps = 13750, // 13.75ns
++ .trp_ps = 13750, // 13.75ns
++ .tras_ps = 32000, // 32ns
++
++ .trfc1_ps = 350000, // 350ns,
++ .trfc2_ps = 260000, // 260ns
++ .trfc4_ps = 160000, // 160ns
++ .trrds_ps = 5300, // min: max(4CK or 5.3ns)
++ .trrdl_ps = 6400, // min: max(4CK or 6.4ns)
++ .tccdl_ps = 5000, // min: max(4CK or 5ns)
++ .trfc_slr_ps = 0,
++
++ .trc_ps = 45750, // tras + trp 45.75ns
++ .twr_ps = 15000, // 15ns
++
++ .refresh_rate_ps = 7800000, // 1x mode 7.8us for standard temperature range (TODO: pick correct range based on temperature?!)
++ // .extended_op_srt = 0,
++
++ // .rcw = {}, // only for registered dimm
++ .dq_mapping = {
++ 0x00,
++ 0x20,
++ 0x00,
++ 0x20,
++ 0x00,
++ 0x20,
++ 0x00,
++ 0x20,
++ 0x00,
++ 0x20,
++ 0x00,
++ 0x20,
++ 0x00,
++ 0x20,
++ 0x00,
++ 0x20,
++ 0x00,
++ 0x20,
++ },
++ .dq_mapping_ors = 1,
++};
++#endif /* CONFIG_DDR_NODIMM == 2 || CONFIG_DDR_NODIMM == 3 */
++
++int ddr_get_ddr_params(struct dimm_params *pdimm,
++ struct ddr_conf *conf)
++{
++ // channel 1
++ conf->dimm_in_use[0] = 1;
++ memcpy(&pdimm[0], &static_dimm, sizeof(struct dimm_params));
++
++#if defined(CONFIG_DDR_NODIMM_CH2)
++ // channel 2
++ conf->dimm_in_use[1] = 1; // enable (module on) channel 2
++ memcpy(&pdimm[1], &static_dimm, sizeof(struct dimm_params));
++
++ /* 2 modules */
++ return 0x3;
++#else
++ /* 1 module */
++ return 0x1;
++#endif /* defined(CONFIG_DDR_NODIMM_CH2) */
++}
++#endif /* defined(CONFIG_DDR_NODIMM) */
++
++int ddr_board_options(struct ddr_info *priv)
++{
++ struct memctl_opt *popts = &priv->opt;
++ const struct ddr_conf *conf = &priv->conf;
++
++ popts->vref_dimm = U(0x24); /* range 1, 83.4% */
++ popts->rtt_override = 0U;
++ popts->rtt_park = U(240);
++ popts->otf_burst_chop_en = 0;
++ popts->burst_length = U(DDR_BL8);
++ popts->trwt_override = 0U;
++ popts->bstopre = 0U; /* auto precharge */
++ popts->addr_hash = 1;
++ popts->caslat_override = 0; // TODO: why is this set by default?!
++ popts->caslat_override_value = 0; // TODO: why is this set by default?!
++ popts->auto_self_refresh_en = 1;
++ popts->output_driver_impedance = 0; // 34 Ohm
++ popts->twot_en = 0;
++ popts->threet_en = 0;
++ popts->addt_lat_override = 0; // TODO: why is this set by default?!
++ popts->addt_lat_override_value = 0; // TODO: why is this set by default?!
++ popts->phy_atx_impedance = 30;
++ popts->skip2d = 0;
++
++ /* Set ODT impedance on PHY side */
++ switch (conf->cs_on_dimm[1]) {
++ case 0xc: /* Two slots dual rank */
++ case 0x4: /* Two slots single rank, not valid for interleaving */
++ popts->trwt = U(0xf);
++ popts->twrt = U(0x7);
++ popts->trrt = U(0x7);
++ popts->twwt = U(0x7);
++ popts->vref_phy = U(0x6B); /* 83.6% */
++ popts->odt = U(60);
++ popts->phy_tx_impedance = U(28);
++ break;
++ case 0: /* One slot used */
++ default:
++ popts->trwt = U(0x3);
++ popts->twrt = U(0x3);
++ popts->trrt = U(0x3);
++ popts->twwt = U(0x3);
++ popts->vref_phy = U(0x60); /* 75% */
++ popts->odt = U(48);
++ popts->phy_tx_impedance = U(28);
++ break;
++ }
++
++ return 0;
++}
++
++long long init_ddr(void)
++{
++ int spd_addr[] = { 0x51, 0x00, 0x53, 0x00 };
++ struct ddr_info info;
++ struct sysinfo sys;
++ long long dram_size;
++
++ zeromem(&sys, sizeof(sys));
++ if (get_clocks(&sys) != 0) {
++ ERROR("System clocks are not set\n");
++ panic();
++ }
++ debug("platform clock %lu\n", sys.freq_platform);
++ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
++ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
++
++ zeromem(&info, sizeof(info));
++
++ /* Set two DDRC. Unused DDRC will be removed automatically. */
++ info.num_ctlrs = NUM_OF_DDRC;
++ info.spd_addr = spd_addr;
++ info.ddr[0] = (void *)NXP_DDR_ADDR;
++ info.ddr[1] = (void *)NXP_DDR2_ADDR;
++ info.phy[0] = (void *)NXP_DDR_PHY1_ADDR;
++ info.phy[1] = (void *)NXP_DDR_PHY2_ADDR;
++ info.clk = get_ddr_freq(&sys, 0);
++ info.img_loadr = load_img;
++ info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER;
++ if (info.clk == 0) {
++ info.clk = get_ddr_freq(&sys, 1);
++ }
++ info.dimm_on_ctlr = DDRC_NUM_DIMM;
++
++ info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED;
++
++ dram_size = dram_init(&info
++#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
++ , NXP_CCN_HN_F_0_ADDR
++#endif
++ );
++
++
++ if (dram_size < 0) {
++ ERROR("DDR init failed.\n");
++ }
++
++ return dram_size;
++}
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/plat_def.h b/plat/nxp/soc-lx2160a/lx2160acex6/plat_def.h
+new file mode 100644
+index 000000000..02f51e74d
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2160acex6/plat_def.h
+@@ -0,0 +1,105 @@
++/*
++ * Copyright 2021 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#ifndef PLAT_DEF_H
++#define PLAT_DEF_H
++
++#include <arch.h>
++#include <cortex_a72.h>
++/* Required without TBBR.
++ * To include the defines for DDR PHY
++ * Images.
++ */
++#include <tbbr_img_def.h>
++
++#include <policy.h>
++#include <soc.h>
++
++#if defined(IMAGE_BL31)
++#define LS_SYS_TIMCTL_BASE 0x2890000
++#define PLAT_LS_NSTIMER_FRAME_ID 0
++#define LS_CONFIG_CNTACR 1
++#endif
++
++#define NXP_SYSCLK_FREQ 100000000
++#define NXP_DDRCLK_FREQ 100000000
++
++/* UART related definition */
++#define NXP_CONSOLE_ADDR NXP_UART_ADDR
++#define NXP_CONSOLE_BAUDRATE 115200
++
++/* Size of cacheable stacks */
++#if defined(IMAGE_BL2)
++#if defined(TRUSTED_BOARD_BOOT)
++#define PLATFORM_STACK_SIZE 0x2000
++#else
++#define PLATFORM_STACK_SIZE 0x1000
++#endif
++#elif defined(IMAGE_BL31)
++#define PLATFORM_STACK_SIZE 0x1000
++#endif
++
++/* SD block buffer */
++#define NXP_SD_BLOCK_BUF_SIZE (0x8000)
++#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
++ - NXP_SD_BLOCK_BUF_SIZE)
++
++#ifdef SD_BOOT
++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
++ - NXP_SD_BLOCK_BUF_SIZE)
++#else
++#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
++#endif
++
++/* IO defines as needed by IO driver framework */
++#define MAX_IO_DEVICES 4
++#define MAX_IO_BLOCK_DEVICES 1
++#define MAX_IO_HANDLES 4
++
++#define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ)
++
++/*
++ * FIP image defines - Offset at which FIP Image would be present
++ * Image would include Bl31 , Bl33 and Bl32 (optional)
++ */
++#ifdef POLICY_FUSE_PROVISION
++#define MAX_FIP_DEVICES 3
++#endif
++
++#ifndef MAX_FIP_DEVICES
++#define MAX_FIP_DEVICES 2
++#endif
++
++/*
++ * ID of the secure physical generic timer interrupt used by the BL32.
++ */
++#define BL32_IRQ_SEC_PHY_TIMER 29
++
++#define BL31_WDOG_SEC 89
++
++#define BL31_NS_WDOG_WS1 108
++
++/*
++ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
++ * terminology. On a GICv2 system or mode, the lists will be merged and treated
++ * as Group 0 interrupts.
++ */
++#define PLAT_LS_G1S_IRQ_PROPS(grp) \
++ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
++ GIC_INTR_CFG_EDGE)
++
++/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
++#define NXP_IRQ_SEC_SGI_7 15
++
++#define PLAT_LS_G0_IRQ_PROPS(grp) \
++ INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
++ GIC_INTR_CFG_EDGE), \
++ INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \
++ GIC_INTR_CFG_EDGE), \
++ INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
++ GIC_INTR_CFG_LEVEL)
++#endif
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/platform.c b/plat/nxp/soc-lx2160a/lx2160acex6/platform.c
+new file mode 100644
+index 000000000..b00adb51d
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2160acex6/platform.c
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2021 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#include <plat_common.h>
++
++#pragma weak board_enable_povdd
++#pragma weak board_disable_povdd
++
++bool board_enable_povdd(void)
++{
++#ifdef CONFIG_POVDD_ENABLE
++ return true;
++#else
++ return false;
++#endif
++}
++
++bool board_disable_povdd(void)
++{
++#ifdef CONFIG_POVDD_ENABLE
++ return true;
++#else
++ return false;
++#endif
++}
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk b/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk
+new file mode 100644
+index 000000000..d01a41ea6
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk
+@@ -0,0 +1,67 @@
++#
++# Copyright 2021 NXP
++#
++# SPDX-License-Identifier: BSD-3-Clause
++#
++
++# board-specific build parameters
++
++BOOT_MODE ?= flexspi_nor
++BOARD ?= lx2160acex6
++POVDD_ENABLE := no
++NXP_COINED_BB := no
++
++ # DDR Compilation Configs
++NUM_OF_DDRC := 2
++DDRC_NUM_DIMM := 2
++DDRC_NUM_CS := 4
++DDR_ECC_EN := yes
++ #enable address decoding feature
++DDR_ADDR_DEC := yes
++APPLY_MAX_CDD := yes
++
++# Mock SPD:
++# - 0: disable mock spd
++# - 2: 2 x 5 x MT40A1G16TB-062E IT:F PCB v1.1
++# - 3: 2 x 5 x MT40A1G16TB-062E IT:F PCB v1.2 (with ECC)
++CONFIG_DDR_NODIMM := 0
++
++# S5 GPIO
++LX2160A_S5_GPIO_ADDR := NXP_GPIO3_ADDR
++LX2160A_S5_GPIO := 0
++
++# I2C Bus Flushing: IIC1
++LX2160_FLUSH_IIC := 1,
++# I2C Mux Flushing: IIC1: PCA9547 at 77: Channel 0 (SPD EEPROM)
++LX2160_FLUSH_IIC_MUX := { 1, 0x77, 0x01 },
++
++# DDR Errata
++ERRATA_DDR_A011396 := 1
++ERRATA_DDR_A050450 := 1
++
++ # On-Board Flash Details
++FLASH_TYPE := MT35XU512A
++XSPI_FLASH_SZ := 0x10000000
++NXP_XSPI_NOR_UNIT_SIZE := 0x20000
++BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000
++# CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This
++# config is enabled for future use cases.
++FSPI_ERASE_4K := 0
++
++ # Platform specific features.
++WARM_BOOT := no
++
++ # Adding Platform files build files
++BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
++ ${BOARD_PATH}/platform.c
++
++SUPPORTED_BOOT_MODE := flexspi_nor \
++ sd \
++ emmc \
++ auto
++
++# Adding platform board build info
++include plat/nxp/common/plat_make_helper/plat_common_def.mk
++
++ # Adding SoC build info
++include plat/nxp/soc-lx2160a/soc.mk
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/platform_def.h b/plat/nxp/soc-lx2160a/lx2160acex6/platform_def.h
+new file mode 100644
+index 000000000..666099800
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2160acex6/platform_def.h
+@@ -0,0 +1,14 @@
++/*
++ * Copyright 2021 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#ifndef PLATFORM_DEF_H
++#define PLATFORM_DEF_H
++
++#include "plat_def.h"
++#include "plat_default_def.h"
++
++#endif
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/policy.h b/plat/nxp/soc-lx2160a/lx2160acex6/policy.h
+new file mode 100644
+index 000000000..19ad6dbec
+--- /dev/null
++++ b/plat/nxp/soc-lx2160a/lx2160acex6/policy.h
+@@ -0,0 +1,38 @@
++/*
++ * Copyright 2021 NXP
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ *
++ */
++
++#ifndef POLICY_H
++#define POLICY_H
++
++/* Following defines affect the PLATFORM SECURITY POLICY */
++
++/* set this to 0x0 if the platform is not using/responding to ECC errors
++ * set this to 0x1 if ECC is being used (we have to do some init)
++ */
++#define POLICY_USING_ECC 0x0
++
++/* Set this to 0x0 to leave the default SMMU page size in sACR
++ * Set this to 0x1 to change the SMMU page size to 64K
++ */
++#define POLICY_SMMU_PAGESZ_64K 0x1
++
++/*
++ * POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I
++ * POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7
++ * POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23
++ */
++#define POLICY_PERF_WRIOP 0
++
++/*
++ * set this to '1' if the debug clocks need to remain enabled during
++ * system entry to low-power (LPM20) - this should only be necessary
++ * for testing and NEVER set for normal production
++ */
++#define POLICY_DEBUG_ENABLE 0
++
++
++#endif /* POLICY_H */
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0016-psci-add-build-time-flag-to-disable-SYSTEM_OFF-funct.patch b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0016-psci-add-build-time-flag-to-disable-SYSTEM_OFF-funct.patch
new file mode 100644
index 0000000000..416c3d509e
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/arm-trusted-firmware/0016-psci-add-build-time-flag-to-disable-SYSTEM_OFF-funct.patch
@@ -0,0 +1,66 @@
+From 77fc969e546ffdb9e369ff5a926b770c035f7522 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sat, 9 Aug 2025 17:50:40 +0200
+Subject: [PATCH] psci: add build-time flag to disable SYSTEM_OFF function
+
+Add support for build-time flag DISABLE_PSCI_SYSTEM_OFF to remove
+support for SYSTEM_OFF from psci, which can be used to prevent operating
+systems from powering off the system.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ Makefile | 2 ++
+ make_helpers/defaults.mk | 4 ++++
+ plat/nxp/common/psci/include/plat_psci.h | 4 ++++
+ 3 files changed, 10 insertions(+)
+
+diff --git a/Makefile b/Makefile
+index ea5701347..12d92fc7e 100644
+--- a/Makefile
++++ b/Makefile
+@@ -1238,6 +1238,7 @@ $(eval $(call assert_booleans,\
+ PSA_CRYPTO \
+ ENABLE_CONSOLE_GETC \
+ INIT_UNUSED_NS_EL2 \
++ DISABLE_S5 \
+ )))
+
+ # Numeric_Flags
+@@ -1432,6 +1433,7 @@ $(eval $(call add_defines,\
+ PSA_CRYPTO \
+ ENABLE_CONSOLE_GETC \
+ INIT_UNUSED_NS_EL2 \
++ DISABLE_S5 \
+ )))
+
+ ifeq (${SANITIZE_UB},trap)
+diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
+index ec2a32767..bffd922dc 100644
+--- a/make_helpers/defaults.mk
++++ b/make_helpers/defaults.mk
+@@ -377,3 +377,7 @@ ENABLE_CONSOLE_GETC := 0
+ # functions must be enabled by platforms if they require it.
+ # Disabled by default.
+ INIT_UNUSED_NS_EL2 := 0
++
++# Build option to disable S5 state.
++# Disabled by default.
++DISABLE_S5 := 0
+diff --git a/plat/nxp/common/psci/include/plat_psci.h b/plat/nxp/common/psci/include/plat_psci.h
+index 7fc48fb73..d26602c2a 100644
+--- a/plat/nxp/common/psci/include/plat_psci.h
++++ b/plat/nxp/common/psci/include/plat_psci.h
+@@ -101,6 +101,10 @@
+ #define SOC_SYSTEM_PWR_DWN 0x1
+ #endif
+
++#if DISABLE_S5
++#define SOC_SYSTEM_OFF 0x0
++#endif
++
+ #ifndef SOC_SYSTEM_OFF
+ #define SOC_SYSTEM_OFF 0x1
+ #endif
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/linux/0001-arm64-dts-freescale-Add-support-for-LX2162-SoM-Clear.patch b/board/solidrun/lx2160acex7/patches/linux/0001-arm64-dts-freescale-Add-support-for-LX2162-SoM-Clear.patch
new file mode 100644
index 0000000000..cc6eeda17f
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/linux/0001-arm64-dts-freescale-Add-support-for-LX2162-SoM-Clear.patch
@@ -0,0 +1,522 @@
+From ec7eefbeacc6516a1f77a8c85f9b21efe88cce4e Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sun, 1 Oct 2023 12:32:59 +0200
+Subject: [PATCH 01/13] arm64: dts: freescale: Add support for LX2162 SoM &
+ Clearfog Board
+
+Add support for the SolidRun LX2162A System on Module (SoM), and the
+Clearfog evaluation board.
+
+The SoM has few software-controllable features:
+- AR8035 Ethernet PHY
+- eMMC
+- SPI Flash
+- fan controller
+- various eeproms
+
+The Clearfog evaluation board provides:
+- microSD connector
+- USB-A
+- 2x 10Gbps SFP+
+- 2x 25Gbps SFP+ with a retimer
+- 8x 2.5Gbps RJ45
+- 2x mPCI (assembly option / disables 2xRJ45)
+
+The 8x RJ45 ports are connected with an 8-port PHY: Marvell 88E2580
+supporting up to 5Gbps, while SoC and magnetics are limited to 2.5Gbps.
+
+However 2500 speed is untested due to documentation and drivier
+limitations. To avoid confusion the phy nodes have been explicitly
+limited to 1000 for now.
+
+The PCI nodes are disabled, but explicitly added to mark that this board
+can have pci.
+It is expected that the bootloader will patch the status property
+"okay" and disable 2x RJ45 ports, according to active serdes configuration.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+Signed-off-by: Shawn Guo <shawnguo at kernel.org>
+---
+ arch/arm64/boot/dts/freescale/Makefile | 1 +
+ .../dts/freescale/fsl-lx2162a-clearfog.dts | 376 ++++++++++++++++++
+ .../dts/freescale/fsl-lx2162a-sr-som.dtsi | 73 ++++
+ 3 files changed, 450 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
+
+diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
+index efe32533733e..59375a2edb5a 100644
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -46,6 +46,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-clearfog.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb
+
+ fsl-ls1028a-qds-13bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-13bb.dtbo
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+new file mode 100644
+index 000000000000..9f88583aa25e
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+@@ -0,0 +1,376 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Device Tree file for LX2162A Clearfog
++//
++// Copyright 2023 Josua Mayer <josua at solid-run.com>
++
++/dts-v1/;
++
++#include "fsl-lx2160a.dtsi"
++#include "fsl-lx2162a-sr-som.dtsi"
++
++/ {
++ model = "SolidRun LX2162A Clearfog";
++ compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";
++
++ aliases {
++ crypto = &crypto;
++ i2c0 = &i2c0;
++ i2c1 = &i2c2;
++ i2c2 = &i2c4;
++ i2c3 = &sfp_i2c0;
++ i2c4 = &sfp_i2c1;
++ i2c5 = &sfp_i2c2;
++ i2c6 = &sfp_i2c3;
++ i2c7 = &mpcie1_i2c;
++ i2c8 = &mpcie0_i2c;
++ i2c9 = &pcieclk_i2c;
++ mmc0 = &esdhc0;
++ mmc1 = &esdhc1;
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ led_sfp_at: led-sfp-at {
++ gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
++ default-state = "off";
++ };
++
++ led_sfp_ab: led-sfp-ab {
++ gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
++ default-state = "off";
++ };
++
++ led_sfp_bt: led-sfp-bt {
++ gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
++ default-state = "off";
++ };
++
++ led_sfp_bb: led-sfp-bb {
++ gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
++ default-state = "off";
++ };
++ };
++
++ sfp_at: sfp-at {
++ compatible = "sff,sfp";
++ i2c-bus = <&sfp_i2c0>;
++ mod-def0-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */
++ maximum-power-milliwatt = <2000>;
++ };
++
++ sfp_ab: sfp-ab {
++ compatible = "sff,sfp";
++ i2c-bus = <&sfp_i2c1>;
++ mod-def0-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */
++ maximum-power-milliwatt = <2000>;
++ };
++
++ sfp_bt: sfp-bt {
++ compatible = "sff,sfp";
++ i2c-bus = <&sfp_i2c2>;
++ mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */
++ maximum-power-milliwatt = <2000>;
++ };
++
++ sfp_bb: sfp-bb {
++ compatible = "sff,sfp";
++ i2c-bus = <&sfp_i2c3>;
++ mod-def0-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */
++ maximum-power-milliwatt = <2000>;
++ };
++};
++
++&dpmac3 {
++ sfp = <&sfp_at>;
++ managed = "in-band-status";
++ phys = <&serdes_1 7>;
++};
++
++&dpmac4 {
++ sfp = <&sfp_ab>;
++ managed = "in-band-status";
++ phys = <&serdes_1 6>;
++};
++
++&dpmac5 {
++ sfp = <&sfp_bt>;
++ managed = "in-band-status";
++ phys = <&serdes_1 5>;
++};
++
++&dpmac6 {
++ sfp = <&sfp_bb>;
++ managed = "in-band-status";
++ phys = <&serdes_1 4>;
++};
++
++&dpmac11 {
++ phys = <&serdes_2 0>;
++ phy-handle = <ðernet_phy3>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac12 {
++ phys = <&serdes_2 1>;
++ phy-handle = <ðernet_phy1>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac13 {
++ phys = <&serdes_2 6>;
++ phy-handle = <ðernet_phy6>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac14 {
++ phys = <&serdes_2 7>;
++ phy-handle = <ðernet_phy8>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac15 {
++ phys = <&serdes_2 4>;
++ phy-handle = <ðernet_phy4>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac16 {
++ phys = <&serdes_2 5>;
++ phy-handle = <ðernet_phy2>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac17 {
++ /* override connection to on-SoM phy */
++ /delete-property/ phy-handle;
++ /delete-property/ phy-connection-type;
++
++ phys = <&serdes_2 2>;
++ phy-handle = <ðernet_phy5>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac18 {
++ phys = <&serdes_2 3>;
++ phy-handle = <ðernet_phy7>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&emdio1 {
++ ethernet_phy1: ethernet-phy at 8 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <8>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy2: ethernet-phy at 9 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <9>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy3: ethernet-phy at 10 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <10>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy4: ethernet-phy at 11 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <11>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy5: ethernet-phy at 12 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <12>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy6: ethernet-phy at 13 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <13>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy7: ethernet-phy at 14 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <14>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy8: ethernet-phy at 15 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <15>;
++ max-speed = <1000>;
++ };
++};
++
++&esdhc0 {
++ sd-uhs-sdr104;
++ sd-uhs-sdr50;
++ sd-uhs-sdr25;
++ sd-uhs-sdr12;
++ status = "okay";
++};
++
++ðernet_phy0 {
++ /*
++ * SoM has a phy at address 1 connected to SoC Ethernet Controller 1.
++ * It competes for WRIOP MAC17, and no connector has been wired.
++ */
++ status = "disabled";
++};
++
++&i2c2 {
++ status = "okay";
++
++ /* retimer at 18 */
++
++ i2c-mux at 70 {
++ compatible = "nxp,pca9546";
++ reg = <0x70>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ i2c-mux-idle-disconnect;
++
++ sfp_i2c0: i2c at 0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++ };
++
++ sfp_i2c1: i2c at 1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++ };
++
++ sfp_i2c2: i2c at 2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++ };
++
++ sfp_i2c3: i2c at 3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++ };
++ };
++
++ i2c-mux at 71 {
++ compatible = "nxp,pca9546";
++ reg = <0x71>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ i2c-mux-idle-disconnect;
++
++ mpcie1_i2c: i2c at 0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++ };
++
++ mpcie0_i2c: i2c at 1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++ };
++
++ pcieclk_i2c: i2c at 2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++
++ /* clock-controller at 6b */
++ };
++ };
++};
++
++&pcie3 {
++ status = "disabled";
++};
++
++&pcie4 {
++ status = "disabled";
++};
++
++&pcs_mdio3 {
++ status = "okay";
++};
++
++&pcs_mdio4 {
++ status = "okay";
++};
++
++&pcs_mdio5 {
++ status = "okay";
++};
++
++&pcs_mdio6 {
++ status = "okay";
++};
++
++&pcs_mdio11 {
++ status = "okay";
++};
++
++&pcs_mdio12 {
++ status = "okay";
++};
++
++&pcs_mdio13 {
++ status = "okay";
++};
++
++&pcs_mdio14 {
++ status = "okay";
++};
++
++&pcs_mdio15 {
++ status = "okay";
++};
++
++&pcs_mdio16 {
++ status = "okay";
++};
++
++&pcs_mdio17 {
++ status = "okay";
++};
++
++&pcs_mdio18 {
++ status = "okay";
++};
++
++&serdes_1 {
++ status = "okay";
++};
++
++&serdes_2 {
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&usb0 {
++ status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
+new file mode 100644
+index 000000000000..0580ea30cfbc
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
+@@ -0,0 +1,73 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Device Tree file for LX2162A-SOM
++//
++// Copyright 2021 Rabeeh Khoury <rabeeh at solid-run.com>
++// Copyright 2023 Josua Mayer <josua at solid-run.com>
++
++&crypto {
++ status = "okay";
++};
++
++&dpmac17 {
++ phy-handle = <ðernet_phy0>;
++ phy-connection-type = "rgmii-id";
++};
++
++&emdio1 {
++ status = "okay";
++
++ ethernet_phy0: ethernet-phy at 1 {
++ reg = <1>;
++ };
++};
++
++&esdhc1 {
++ bus-width = <8>;
++ mmc-hs200-1_8v;
++ mmc-hs400-1_8v;
++ status = "okay";
++};
++
++&fspi {
++ status = "okay";
++
++ flash at 0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ m25p,fast-read;
++ spi-max-frequency = <50000000>;
++ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
++ spi-rx-bus-width = <8>;
++ spi-tx-bus-width = <1>;
++ };
++};
++
++&i2c0 {
++ status = "okay";
++
++ fan-controller at 18 {
++ compatible = "ti,amc6821";
++ reg = <0x18>;
++ };
++
++ ddr_spd: eeprom at 51 {
++ compatible = "st,24c02", "atmel,24c02";
++ reg = <0x51>;
++ read-only;
++ };
++
++ config_eeprom: eeprom at 57 {
++ compatible = "st,24c02", "atmel,24c02";
++ reg = <0x57>;
++ };
++};
++
++&i2c4 {
++ status = "okay";
++
++ variable_eeprom: eeprom at 54 {
++ compatible = "st,24c2048", "atmel,24c2048";
++ reg = <0x54>;
++ };
++};
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/linux/0002-arm64-dts-fsl-lx2162a-som-add-description-for-rtc.patch b/board/solidrun/lx2160acex7/patches/linux/0002-arm64-dts-fsl-lx2162a-som-add-description-for-rtc.patch
new file mode 100644
index 0000000000..be0010f324
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/linux/0002-arm64-dts-fsl-lx2162a-som-add-description-for-rtc.patch
@@ -0,0 +1,34 @@
+From 29e09ee374235ae096344cdd62f80989a3ec2c71 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Tue, 12 Mar 2024 20:56:54 +0100
+Subject: [PATCH 02/13] arm64: dts: fsl-lx2162a-som: add description for rtc
+
+SolidRun LX2162A SoM has an RTC on bus IIC6 (dts i2c5).
+Enable this bus and add description for the rtc.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+Signed-off-by: Shawn Guo <shawnguo at kernel.org>
+---
+ arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
+index 0580ea30cfbc..e914291e63a1 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
+@@ -71,3 +71,12 @@ variable_eeprom: eeprom at 54 {
+ reg = <0x54>;
+ };
+ };
++
++&i2c5 {
++ status = "okay";
++
++ rtc at 6f {
++ compatible = "microchip,mcp7940x";
++ reg = <0x6f>;
++ };
++};
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/linux/0003-arm64-dts-fsl-lx2162a-clearfog-add-alias-for-i2c-bus.patch b/board/solidrun/lx2160acex7/patches/linux/0003-arm64-dts-fsl-lx2162a-clearfog-add-alias-for-i2c-bus.patch
new file mode 100644
index 0000000000..feff43841b
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/linux/0003-arm64-dts-fsl-lx2162a-clearfog-add-alias-for-i2c-bus.patch
@@ -0,0 +1,32 @@
+From f9752ad55b1340bdab2df082efe7131db9f8da75 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Tue, 12 Mar 2024 20:56:55 +0100
+Subject: [PATCH 03/13] arm64: dts: fsl-lx2162a-clearfog: add alias for i2c bus
+ iic6
+
+SoM dts has enabled i2c bus IIC6 (dts i2c5), but defines no aliases.
+
+LX2162A Clearfog dts has aliases for all i2c buses to ensure predictable
+numbering for userspace. Add an additional alias for this extra bus.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+Signed-off-by: Shawn Guo <shawnguo at kernel.org>
+---
+ arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+index 9f88583aa25e..eafef8718a0f 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+@@ -25,6 +25,7 @@ aliases {
+ i2c7 = &mpcie1_i2c;
+ i2c8 = &mpcie0_i2c;
+ i2c9 = &pcieclk_i2c;
++ i2c10 = &i2c5;
+ mmc0 = &esdhc0;
+ mmc1 = &esdhc1;
+ serial0 = &uart0;
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/linux/0004-arm64-dts-lx2160a-cex7-add-interrupts-for-rtc-and-et.patch b/board/solidrun/lx2160acex7/patches/linux/0004-arm64-dts-lx2160a-cex7-add-interrupts-for-rtc-and-et.patch
new file mode 100644
index 0000000000..a314b3bfee
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/linux/0004-arm64-dts-lx2160a-cex7-add-interrupts-for-rtc-and-et.patch
@@ -0,0 +1,39 @@
+From b9c71f412bc8ce51383d230756fa40118d5cb31b Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Mon, 25 Aug 2025 19:19:38 +0200
+Subject: [PATCH 04/13] arm64: dts: lx2160a-cex7: add interrupts for rtc and
+ ethernet phy
+
+SolidRun LX2160A CEX-7 module has interrupts wired for both the rtc and
+ethernet phy.
+
+Add description for those interrupts to the rtc and phy nodes.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+index d32a52ab00a4..8f9007ca4941 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+@@ -41,6 +41,7 @@ &emdio1 {
+ rgmii_phy1: ethernet-phy at 1 {
+ reg = <1>;
+ qca,smarteee-tw-us-1g = <24>;
++ interrupts-extended = <&gpio2 4 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+
+@@ -159,6 +160,7 @@ &i2c4 {
+ rtc at 51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
++ interrupts-extended = <&gpio2 8 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/linux/0005-arm64-dts-lx2160a-clearfog-itx-enable-pcie-nodes-for.patch b/board/solidrun/lx2160acex7/patches/linux/0005-arm64-dts-lx2160a-clearfog-itx-enable-pcie-nodes-for.patch
new file mode 100644
index 0000000000..6fe760c78e
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/linux/0005-arm64-dts-lx2160a-clearfog-itx-enable-pcie-nodes-for.patch
@@ -0,0 +1,40 @@
+From ac06d0c2e7787ccdcb693445a43cb21b29865b49 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sun, 20 Oct 2024 14:19:43 +0200
+Subject: [PATCH 05/13] arm64: dts: lx2160a-clearfog-itx: enable pcie nodes for
+ x4 and x8 slots
+
+SolidRun Clearfog CX and Honeycomb have LX2160A PEX3 and PEX5 exposed on
+physical connectors.
+Vendor U-Boot used to patch status properties such that it went
+undiscovered these nodes have their status set disabled.
+
+Set status okay for pcie3 and pcie5 nodes.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ .../boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+index a7dcbecc1f41..af6258b2fe82 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+@@ -96,6 +96,14 @@ &esdhc0 {
+ status = "okay";
+ };
+
++&pcie3 {
++ status = "okay";
++};
++
++&pcie5 {
++ status = "okay";
++};
++
+ &pcs_mdio7 {
+ status = "okay";
+ };
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/linux/0006-rtc-pcf2127-clear-minute-second-interrupt.patch b/board/solidrun/lx2160acex7/patches/linux/0006-rtc-pcf2127-clear-minute-second-interrupt.patch
new file mode 100644
index 0000000000..fbdabb66b4
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/linux/0006-rtc-pcf2127-clear-minute-second-interrupt.patch
@@ -0,0 +1,62 @@
+From 082f9738584eee0b9b09cc03e0e5a2ecb4c2f164 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Mon, 25 Aug 2025 18:59:33 +0200
+Subject: [PATCH 06/13] rtc: pcf2127: clear minute/second interrupt
+
+PCF2127 can generate interrupt every full second or minute configured
+from control and status register 1, bits MI (1) and SI (0).
+
+On interrupt control register 2 bit MSF (7) is set and must be cleared
+to continue normal operation.
+
+While the driver never enables this interrupt on its own, users or
+firmware may do so - e.g. as an easy way to test the interrupt.
+
+Add preprocessor definition for MSF bit and include it in the irq
+bitmask to ensure minute and second interrupts are cleared when fired.
+
+This fixes an issue where the rtc enters a test mode and becomes
+unresponsive after a second interrupt has fired and is not cleared in
+time. In this state register writes to control registers have no
+effect and the interrupt line is kept asserted [1]:
+
+[1] userspace commands to put rtc into unresponsive state:
+$ i2cget -f -y 2 0x51 0x00
+0x04
+$ i2cset -f -y 2 0x51 0x00 0x05 # set bit 0 SI
+$ i2cget -f -y 2 0x51 0x00
+0x84 # bit 8 EXT_TEST set
+$ i2cset -f -y 2 0x51 0x00 0x05 # try overwrite control register
+$ i2cget -f -y 2 0x51 0x00
+0x84 # no change
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ drivers/rtc/rtc-pcf2127.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
+index 9c04c4e1a49c..083d402e96f9 100644
+--- a/drivers/rtc/rtc-pcf2127.c
++++ b/drivers/rtc/rtc-pcf2127.c
+@@ -41,6 +41,7 @@
+ #define PCF2127_BIT_CTRL2_AF BIT(4)
+ #define PCF2127_BIT_CTRL2_TSF2 BIT(5)
+ #define PCF2127_BIT_CTRL2_WDTF BIT(6)
++#define PCF2127_BIT_CTRL2_MSF BIT(7)
+ /* Control register 3 */
+ #define PCF2127_REG_CTRL3 0x02
+ #define PCF2127_BIT_CTRL3_BLIE BIT(0)
+@@ -94,7 +95,8 @@
+ #define PCF2127_CTRL2_IRQ_MASK ( \
+ PCF2127_BIT_CTRL2_AF | \
+ PCF2127_BIT_CTRL2_WDTF | \
+- PCF2127_BIT_CTRL2_TSF2)
++ PCF2127_BIT_CTRL2_TSF2 | \
++ PCF2127_BIT_CTRL2_MSF)
+
+ #define PCF2127_MAX_TS_SUPPORTED 4
+
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/linux/0007-arm64-dts-lx2160a-extend-32-bit-and-add-64-bit-pci-r.patch b/board/solidrun/lx2160acex7/patches/linux/0007-arm64-dts-lx2160a-extend-32-bit-and-add-64-bit-pci-r.patch
new file mode 100644
index 0000000000..fc178b0bca
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/linux/0007-arm64-dts-lx2160a-extend-32-bit-and-add-64-bit-pci-r.patch
@@ -0,0 +1,109 @@
+From 3c5bf50db8001eb410dff3b4f02365feda022929 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Thu, 21 Mar 2024 16:13:19 +0100
+Subject: [PATCH 07/13] arm64: dts: lx2160a: extend 32-bit, and add 64-bit pci
+ regions
+
+LX2160 SoC pci-e controller supports 64-bit memory regions up to 16GB,
+32-bit regions up to 3GB and 16-bit regions up to 64k.
+
+For each pci-e controller:
+- extend the existing 32-bit regions to 3GB size
+- add 16-bit region
+- add 64-bit region
+
+Same memory allocation with similar flags were been tested with UEFI
+and ACPI on pcie3 and pcie5.
+This specific device-tree configuration was tested with nxp lsdk-21.08
+and lf-5.15.71-2.2.0 based u-boot:
+- pcie5 with a Radeon Pro WX2100 with Gnome Desktop
+- pcie3 with an ADATA NVME
+
+Fixes allocation of large, and 64-bit BARs as requested by many pci
+cards, especially graphics processors or AI accelerators, e.g.:
+[ 2.941187] pci 0000:01:00.0: BAR 0: no space for [mem size 0x200000000 64bit pref]
+[ 2.948834] pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x200000000 64bit pref]
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 25 ++++++++++++++-----
+ 1 file changed, 19 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+index 168298cc4dfd..589d1562b1a6 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+@@ -1,3 +1,4 @@
++
+ // SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ //
+ // Device Tree Include file for Layerscape-LX2160A family SoC.
+@@ -1159,7 +1160,9 @@ pcie1: pcie at 3400000 {
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+- ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ ranges = <0x02102000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>, /* 64-Bit - prefetchable */
++ <0x02000200 0x00 0x40000000 0x80 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */
++ <0x01200100 0x00 0x00000000 0x80 0x10000000 0x00 0x00010000>; /* 16-Bit IO Window */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+@@ -1187,7 +1190,9 @@ pcie2: pcie at 3500000 {
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+- ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ ranges = <0x02102000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>, /* 64-Bit - prefetchable */
++ <0x02000200 0x00 0x40000000 0x88 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */
++ <0x01200100 0x00 0x00000000 0x88 0x10000000 0x00 0x00010000>; /* 16-Bit IO Window */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+@@ -1215,7 +1220,9 @@ pcie3: pcie at 3600000 {
+ apio-wins = <256>;
+ ppio-wins = <24>;
+ bus-range = <0x0 0xff>;
+- ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ ranges = <0x02102000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>, /* 64-Bit - prefetchable */
++ <0x02000200 0x00 0x40000000 0x90 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */
++ <0x01200100 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000>; /* 16-Bit IO Window */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+@@ -1243,7 +1250,9 @@ pcie4: pcie at 3700000 {
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+- ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ ranges = <0x02102000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>, /* 64-Bit - prefetchable */
++ <0x02000200 0x00 0x40000000 0x98 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */
++ <0x01200100 0x00 0x00000000 0x98 0x10000000 0x00 0x00010000>; /* 16-Bit IO Window */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+@@ -1271,7 +1280,9 @@ pcie5: pcie at 3800000 {
+ apio-wins = <256>;
+ ppio-wins = <24>;
+ bus-range = <0x0 0xff>;
+- ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ ranges = <0x02102000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>, /* 64-Bit - prefetchable */
++ <0x02000200 0x00 0x40000000 0xa0 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */
++ <0x01200100 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000>; /* 16-Bit IO Window */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+@@ -1299,7 +1310,9 @@ pcie6: pcie at 3900000 {
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+- ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ ranges = <0x02102000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>, /* 64-Bit - prefetchable */
++ <0x02000200 0x00 0x40000000 0xa8 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */
++ <0x01200100 0x00 0x00000000 0xa8 0x10000000 0x00 0x00010000>; /* 16-Bit IO Window */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/linux/0008-phy-lynx-28g-check-return-value-when-calling-lynx_28.patch b/board/solidrun/lx2160acex7/patches/linux/0008-phy-lynx-28g-check-return-value-when-calling-lynx_28.patch
new file mode 100644
index 0000000000..bd99bd1808
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/linux/0008-phy-lynx-28g-check-return-value-when-calling-lynx_28.patch
@@ -0,0 +1,138 @@
+From 074660f91ef6019ac7884b27249a78d5b448ddfb Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Tue, 26 Aug 2025 14:28:16 +0200
+Subject: [PATCH 08/13] phy: lynx-28g: check return value when calling
+ lynx_28g_pll_get
+
+The lynx_28g_pll_get function may return NULL when called with an
+unsupported submode argument.
+
+In the calling code driver authors did not anticipate unsupported modes
+passed through the pcs set_mode function and failed to add null checks.
+
+Check return value at every invocation and return error code where
+possible.
+
+Also print a warning the first time lynx_28g_pll_get returns NULL
+because calling code should validate modes before set.
+
+Fixes null-pointer dereference when set_mode is called for an
+unsupported mode, such as 2.5GBase-T - encountered in a v6.6.52 based
+vendor kernel:
+
+[ 127.019924] fsl_dpaa2_eth dpni.4 eth5: dpmac_set_protocol(2500base-x) = -ENOTSUPP
+[ 127.027451] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000014
+[ 127.036245] Mem abort info:
+[ 127.039044] ESR = 0x0000000096000004
+[ 127.042794] EC = 0x25: DABT (current EL), IL = 32 bits
+[ 127.048107] SET = 0, FnV = 0
+[ 127.051161] EA = 0, S1PTW = 0
+[ 127.054301] FSC = 0x04: level 0 translation fault
+[ 127.059179] Data abort info:
+[ 127.062059] ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
+[ 127.067547] CM = 0, WnR = 0, TnD = 0, TagAccess = 0
+[ 127.072596] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
+[ 127.077907] user pgtable: 4k pages, 48-bit VAs, pgdp=00000020816c9000
+[ 127.084344] [0000000000000014] pgd=0000000000000000, p4d=0000000000000000
+[ 127.091133] Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP
+[ 127.097390] Modules linked in: cfg80211 rfkill fsl_jr_uio caam_jr dpaa2_caam caamkeyblob_desc crypto_engine caamhash_desc onboard_usb_hub caamalg_desc crct10dif_ce libdes caam error at24 rtc_ds1307 rtc_fsl_ftm_alarm nvmem_layerscape_sfp layerscape_edac_mod dm_mod nfnetlink ip_tables
+[ 127.122436] CPU: 5 PID: 96 Comm: kworker/u35:0 Not tainted 6.6.52-g3578ef896722 #10
+[ 127.130083] Hardware name: SolidRun LX2162A Clearfog (DT)
+[ 127.135470] Workqueue: events_power_efficient phylink_resolve
+[ 127.141219] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
+[ 127.148170] pc : lynx_28g_set_lane_mode+0x300/0x818
+[ 127.153041] lr : lynx_28g_set_lane_mode+0x2fc/0x818
+[ 127.157909] sp : ffff8000806f3b80
+[ 127.161212] x29: ffff8000806f3b80 x28: 0000000000000000 x27: 0000000000000000
+[ 127.168340] x26: ffff29d6c11f3098 x25: 0000000000000000 x24: 0000000000000000
+[ 127.175467] x23: ffff29d6c11f31f0 x22: ffff29d6c11f3080 x21: 0000000000000001
+[ 127.182595] x20: ffff29d6c11f4c00 x19: 0000000000000000 x18: 0000000000000006
+[ 127.189722] x17: 4f4e452d203d2029 x16: 782d657361623030 x15: 3532286c6f636f74
+[ 127.196849] x14: 6f72705f7465735f x13: ffffd7a8ff991cc0 x12: 0000000000000acb
+[ 127.203976] x11: 0000000000000399 x10: ffffd7a8ff9e9cc0 x9 : 0000000000000000
+[ 127.211104] x8 : 0000000000000000 x7 : 0000000000000000 x6 : ffff29d6c11f3080
+[ 127.218231] x5 : 0000000000000000 x4 : 0000000040800030 x3 : 000000000000034c
+[ 127.225358] x2 : ffff29d6c11f3080 x1 : 000000000000034c x0 : 0000000000000000
+[ 127.232486] Call trace:
+[ 127.234921] lynx_28g_set_lane_mode+0x300/0x818
+[ 127.239443] lynx_28g_set_mode+0x12c/0x148
+[ 127.243529] phy_set_mode_ext+0x5c/0xa8
+[ 127.247356] lynx_pcs_config+0x64/0x294
+[ 127.251184] phylink_major_config+0x184/0x49c
+[ 127.255532] phylink_resolve+0x2a0/0x5d8
+[ 127.259446] process_one_work+0x138/0x248
+[ 127.263448] worker_thread+0x320/0x438
+[ 127.267187] kthread+0x114/0x118
+[ 127.270406] ret_from_fork+0x10/0x20
+[ 127.273973] Code: 2a1303e1 aa0603e0 97fffd3b aa0003e5 (b9401400)
+[ 127.280055] ---[ end trace 0000000000000000 ]---
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ drivers/phy/freescale/phy-fsl-lynx-28g.c | 28 +++++++++++++++++++-----
+ 1 file changed, 23 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
+index 7be7ebe86704..c00a636338d0 100644
+--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
++++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
+@@ -893,6 +893,10 @@ static struct lynx_28g_pll *lynx_28g_pll_get(struct lynx_28g_priv *priv,
+ return pll;
+ }
+
++ /* no pll supports requested mode, caller should have called
++ * lynx_28g_supports_lane_mode first
++ */
++ dev_WARN_ONCE(priv->dev, 1, "no pll for lane_mode %d\n", mode);
+ return NULL;
+ }
+
+@@ -1403,8 +1407,12 @@ static void lynx_28g_lane_remap_pll(struct lynx_28g_lane *lane,
+ struct lynx_28g_priv *priv = lane->priv;
+ struct lynx_28g_pll *pll;
+
+- /* Switch to the PLL that works with this interface type */
++ /* Find the PLL that works with this interface type */
+ pll = lynx_28g_pll_get(priv, lane_mode);
++ if (unlikely(pll == NULL))
++ return;
++
++ /* Switch to the PLL that works with this interface type */
+ lynx_28g_lane_set_pll(lane, pll);
+
+ /* Choose the portion of clock net to be used on this lane */
+@@ -1571,6 +1579,7 @@ static int lynx_28g_set_lane_mode(struct phy *phy, enum lynx_28g_lane_mode lane_
+ {
+ struct lynx_28g_lane *lane = phy_get_drvdata(phy);
+ struct lynx_28g_priv *priv = lane->priv;
++ struct lynx_28g_pll *pll;
+ bool powered_up = lane->powered_up;
+ bool is_backplane;
+ int err;
+@@ -1607,10 +1616,19 @@ static int lynx_28g_set_lane_mode(struct phy *phy, enum lynx_28g_lane_mode lane_
+ /* 1000Base-KX lanes need their PLL to generate a 312.5 MHz frequency
+ * through EX_DLY_CLK.
+ */
+- if (lane_mode == LANE_MODE_1000BASEKX)
+- lynx_28g_pll_get_ex_dly_clk(lynx_28g_pll_get(priv, lane_mode));
+- else if (lane->mode == LANE_MODE_1000BASEKX)
+- lynx_28g_pll_put_ex_dly_clk(lynx_28g_pll_get(priv, lane->mode));
++ if (lane_mode == LANE_MODE_1000BASEKX) {
++ pll = lynx_28g_pll_get(priv, lane_mode);
++ if (unlikely(pll == NULL))
++ return -EINVAL;
++
++ lynx_28g_pll_get_ex_dly_clk(pll);
++ } else if (lane->mode == LANE_MODE_1000BASEKX) {
++ pll = lynx_28g_pll_get(priv, lane->mode);
++ if (unlikely(pll == NULL))
++ return -EINVAL;
++
++ lynx_28g_pll_put_ex_dly_clk(pll);
++ }
+
+ lane->mode = lane_mode;
+
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/linux/0009-net-phy-marvell10g-add-support-for-88e2580-multi-gig.patch b/board/solidrun/lx2160acex7/patches/linux/0009-net-phy-marvell10g-add-support-for-88e2580-multi-gig.patch
new file mode 100644
index 0000000000..b71858561b
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/linux/0009-net-phy-marvell10g-add-support-for-88e2580-multi-gig.patch
@@ -0,0 +1,177 @@
+From 4c726de9178562721d101bd6f564a2f979bd1d76 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Thu, 3 Nov 2022 17:12:18 +0200
+Subject: [PATCH 09/13] net: phy: marvell10g: add support for 88e2580 multi-gig
+ ethernet phy
+
+The Marvell 88E2580 is an 8-port multi-gigabit phy supporting 10Mbps to
+5GBase-T Ethernet.
+
+Each port is addressed individually on mdio by its own address, and they
+all share the same phy identifier.
+
+Add basic support for the 88E2540 PHY operating each port individually,
+i.e. DXGMII/QXGMII/OXGMII are not implemented.
+
+The PHY supports most registers with 3310 but uses particular values for
+mactype selection.
+
+match_phy_device is not implemented because no incompatible phy id
+collisions are currently known.
+
+get_features is not implemented because the tested 88e2580 phy does not
+need pma_ngbaset_quirk.
+
+Tested on LX2162A Clearfog board with up to 1gbase-t only.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ drivers/net/phy/marvell10g.c | 77 ++++++++++++++++++++++++++++++++++++
+ include/linux/marvell_phy.h | 1 +
+ 2 files changed, 78 insertions(+)
+
+diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
+index d4bb90d76881..cdb931b12844 100644
+--- a/drivers/net/phy/marvell10g.c
++++ b/drivers/net/phy/marvell10g.c
+@@ -113,6 +113,7 @@ enum {
+ MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
+ MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
+ MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
++ MV_V2_2580_PORT_CTRL_MACTYPE_USXGMII = 0x0,
+ MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0,
+ MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1,
+ MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1,
+@@ -702,6 +703,22 @@ static int mv3310_select_mactype(unsigned long *interfaces)
+ return -1;
+ }
+
++static int mv2580_select_mactype(unsigned long *interfaces)
++{
++ /* mv88e2580 supports usxgmii, 10gbase-r with sgmii AN and 10gbase-kr,
++ * rate-matching is not supported.
++ */
++ if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces))
++ return MV_V2_2580_PORT_CTRL_MACTYPE_USXGMII;
++ else if ((test_bit(PHY_INTERFACE_MODE_SGMII, interfaces)) ||
++ (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces)))
++ return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
++ else if (test_bit(PHY_INTERFACE_MODE_10GKR, interfaces))
++ return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN;
++ else
++ return -1;
++}
++
+ static int mv2110_init_interface(struct phy_device *phydev, int mactype)
+ {
+ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
+@@ -768,6 +785,24 @@ static int mv3340_init_interface(struct phy_device *phydev, int mactype)
+ return err;
+ }
+
++static int mv2580_init_interface(struct phy_device *phydev, int mactype)
++{
++ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
++
++ priv->rate_match = false;
++
++ if (mactype == MV_V2_2580_PORT_CTRL_MACTYPE_USXGMII)
++ priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
++ else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER)
++ priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
++ else if(mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN)
++ priv->const_interface = PHY_INTERFACE_MODE_10GKR;
++ else
++ return -EINVAL;
++
++ return 0;
++}
++
+ static int mv3310_config_init(struct phy_device *phydev)
+ {
+ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
+@@ -1157,6 +1192,16 @@ static void mv2111_init_supported_interfaces(unsigned long *mask)
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
+ }
+
++static void mv2580_init_supported_interfaces(unsigned long *mask)
++{
++ __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
++ __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
++ __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
++ __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
++ __set_bit(PHY_INTERFACE_MODE_10GKR, mask);
++ __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
++}
++
+ static const struct mv3310_chip mv3310_type = {
+ .has_downshift = mv3310_has_downshift,
+ .init_supported_interfaces = mv3310_init_supported_interfaces,
+@@ -1207,6 +1252,18 @@ static const struct mv3310_chip mv2111_type = {
+ #endif
+ };
+
++static const struct mv3310_chip mv2580_type = {
++ .init_supported_interfaces = mv2580_init_supported_interfaces,
++ .get_mactype = mv3310_get_mactype,
++ .set_mactype = mv3310_set_mactype,
++ .select_mactype = mv2580_select_mactype,
++ .init_interface = mv2580_init_interface,
++
++#ifdef CONFIG_HWMON
++ .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
++#endif
++};
++
+ static int mv3310_get_number_of_ports(struct phy_device *phydev)
+ {
+ int ret;
+@@ -1417,6 +1474,25 @@ static struct phy_driver mv3310_drivers[] = {
+ .remove = mv3310_remove,
+ .set_loopback = genphy_c45_loopback,
+ },
++ {
++ .phy_id = MARVELL_PHY_ID_88E2580,
++ .phy_id_mask = MARVELL_PHY_ID_MASK,
++ .name = "mv88e2580",
++ .driver_data = &mv2580_type,
++ .probe = mv3310_probe,
++ .suspend = mv3310_suspend,
++ .resume = mv3310_resume,
++ .config_init = mv3310_config_init,
++ .config_aneg = mv3310_config_aneg,
++ .aneg_done = mv3310_aneg_done,
++ .read_status = mv3310_read_status,
++ .get_tunable = mv3310_get_tunable,
++ .set_tunable = mv3310_set_tunable,
++ .remove = mv3310_remove,
++ .set_loopback = genphy_c45_loopback,
++ .get_wol = mv3110_get_wol,
++ .set_wol = mv3110_set_wol,
++ },
+ };
+
+ module_phy_driver(mv3310_drivers);
+@@ -1424,6 +1500,7 @@ module_phy_driver(mv3310_drivers);
+ static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
+ { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
++ { MARVELL_PHY_ID_88E2580, MARVELL_PHY_ID_MASK },
+ { },
+ };
+ MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
+diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
+index 9b54c4f0677f..81e6f7b506a0 100644
+--- a/include/linux/marvell_phy.h
++++ b/include/linux/marvell_phy.h
+@@ -24,6 +24,7 @@
+ #define MARVELL_PHY_ID_88E3016 0x01410e60
+ #define MARVELL_PHY_ID_88X3310 0x002b09a0
+ #define MARVELL_PHY_ID_88E2110 0x002b09b0
++#define MARVELL_PHY_ID_88E2580 0x002b0bc3
+ #define MARVELL_PHY_ID_88X2222 0x01410f10
+ #define MARVELL_PHY_ID_88Q2110 0x002b0980
+
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/linux/0010-net-phy-create-driver-for-ds250df4x10-retimer.patch b/board/solidrun/lx2160acex7/patches/linux/0010-net-phy-create-driver-for-ds250df4x10-retimer.patch
new file mode 100644
index 0000000000..af0cd94ea6
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/linux/0010-net-phy-create-driver-for-ds250df4x10-retimer.patch
@@ -0,0 +1,502 @@
+From a8889bce584f0caa8777eabdb4e5ff45fab9f9e5 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Wed, 12 Oct 2022 18:46:09 +0300
+Subject: [PATCH 10/13] net: phy: create driver for ds250df4x10 retimer
+
+Create driver for the TI DS250DF410 and DS250DF810 retimers.
+Both variants feature either 4 or 8 channels to be configured
+individually from 20.2752 to 25.8Gbps, while also supporting subrates by
+dividing either with 2 or 4.
+
+Configuration is provided to other drivers by implementing a generic phy
+with support for set_mode.
+
+3 standard configurations for 1/10/25G Ethernet are supported:
+- PHY_INTERFACE_MODE_SGMII: 1.25 Gbps
+- PHY_INTERFACE_MODE_10GBASER: 10.3125 Gbps
+- PHY_INTERFACE_MODE_25GBASER: 25.78125Gbps
+
+The driver also hardcodes signal conditioning parameters.
+Future revisions shall read those from device-tree instead.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ drivers/phy/ti/Kconfig | 9 +
+ drivers/phy/ti/Makefile | 1 +
+ drivers/phy/ti/phy-ti-ds250dfx10.c | 432 +++++++++++++++++++++++++++++
+ 3 files changed, 442 insertions(+)
+ create mode 100644 drivers/phy/ti/phy-ti-ds250dfx10.c
+
+diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig
+index af5653f24cbc..4a0fd2a59670 100644
+--- a/drivers/phy/ti/Kconfig
++++ b/drivers/phy/ti/Kconfig
+@@ -84,6 +84,15 @@ config TI_PIPE3
+ This driver interacts with the "OMAP Control PHY Driver" to power
+ on/off the PHY.
+
++config PHY_DS250DFX10
++ tristate "Texas Instruments DS250DFX10 Retimer"
++ depends on OF
++ select GENERIC_PHY
++ help
++ Enable to support runtime configuration of DS250DFX10 retimers.
++ The retimers are modeled as generic PHYs,
++ currently supporting 10 & 25 GBASER link speeds.
++
+ config PHY_TUSB1210
+ tristate "TI TUSB1210 ULPI PHY module"
+ depends on USB_ULPI_BUS
+diff --git a/drivers/phy/ti/Makefile b/drivers/phy/ti/Makefile
+index e68445ddd848..f1459b9e5fab 100644
+--- a/drivers/phy/ti/Makefile
++++ b/drivers/phy/ti/Makefile
+@@ -4,6 +4,7 @@ obj-$(CONFIG_PHY_DM816X_USB) += phy-dm816x-usb.o
+ obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
+ obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
+ obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
++obj-$(CONFIG_PHY_DS250DFX10) += phy-ti-ds250dfx10.o
+ obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
+ obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
+ obj-$(CONFIG_PHY_AM654_SERDES) += phy-am654-serdes.o
+diff --git a/drivers/phy/ti/phy-ti-ds250dfx10.c b/drivers/phy/ti/phy-ti-ds250dfx10.c
+new file mode 100644
+index 000000000000..bab1a29669c3
+--- /dev/null
++++ b/drivers/phy/ti/phy-ti-ds250dfx10.c
+@@ -0,0 +1,432 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Driver for the TI DS250DF410 Retimer
++ *
++ * Copyright (C) 2022-2023 Josua Mayer <josua at solid-run.com>
++ */
++
++#include <linux/i2c.h>
++#include <linux/module.h>
++#include <linux/phy.h>
++#include <linux/phy/phy.h>
++
++#define DS250DF410_REG_CHAN_CONFIG_ID 0xEF
++#define DS250DF410_MASK_CHAN_CONFIG_ID GENMASK(3, 0)
++#define DS250DF410_REG_VERSION 0xF0
++#define DS250DF410_REG_DEVICE_ID 0xF1
++#define DS250DF410_REG_CHAN_VERSION 0xF3
++#define DS250DF410_MASK_CHAN_VERSION GENMASK(7, 4)
++#define DS250DF410_MASK_SHARE_VERSION GENMASK(3, 0)
++
++struct ds250dfx10_phy_priv {
++ struct i2c_client *client;
++ uint8_t channel;
++};
++
++struct ds250dfx10_priv {
++ struct phy *phy[8];
++ struct phy_provider *provider;
++};
++
++static int ds250dfx10_read_register(struct i2c_client *client, uint8_t address, uint8_t *value,
++ uint8_t mask)
++{
++ s32 res;
++
++ res = i2c_smbus_read_byte_data(client, address);
++ if (res < 0) {
++ dev_err(&client->dev, "failed to read register %#04x: %d\n", address,
++ res);
++ return -EIO;
++ }
++
++ *value = res & mask;
++ return 0;
++}
++
++static int ds250dfx10_write_register(struct i2c_client *client, uint8_t address, uint8_t value,
++ uint8_t mask)
++{
++ int ret;
++ uint8_t tmp;
++ s32 res;
++
++ // combine with current value according to mask
++ if (mask != 0xFF) {
++ ret = ds250dfx10_read_register(client, address, &tmp, ~mask);
++ if (ret)
++ return ret;
++
++ value = (value & mask) | tmp;
++ }
++
++ // write new value
++ res = i2c_smbus_write_byte_data(client, address, value);
++ if (res < 0) {
++ dev_err(&client->dev, "failed to write register %#04x=%#04x: %d\n",
++ address, value, res);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static void ds250dfx10_config_1g(struct i2c_client *client, uint8_t channel)
++{
++ int ret = 0;
++
++ // enable smbus access to single channel
++ ret |= ds250dfx10_write_register(client, 0xFF, 0x01, 0x03);
++
++ // select channel
++ ret |= ds250dfx10_write_register(client, 0xFC, 1 << channel, 0xFF);
++
++ // reset channel registers
++ ret |= ds250dfx10_write_register(client, 0x00, 0x04, 0x04);
++
++ // assert cdr
++ ret |= ds250dfx10_write_register(client, 0x0A, 0x0C, 0x0C);
++
++ // set manual data rate override to 1.25Gbps
++ ret |= ds250dfx10_write_register(client, 0x60, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(client, 0x61, 0xb2, 0xFF);
++ ret |= ds250dfx10_write_register(client, 0x62, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(client, 0x63, 0xb2, 0xFF);
++
++ // set maximum ppm delta tolerance
++ ret |= ds250dfx10_write_register(client, 0x64, 0xFF, 0xFF);
++
++ // enable manual divider override
++ ret |= ds250dfx10_write_register(client, 0x09, 0x04, 0x04);
++
++ // set divider to 16
++ ret |= ds250dfx10_write_register(client, 0x18, 0x40, 0x70);
++
++ // enable pre- and post-fir
++ ret |= ds250dfx10_write_register(client, 0x3D, 0x80, 0x80);
++
++ // set main cursor magnitude +15
++ ret |= ds250dfx10_write_register(client, 0x3D, 0x00, 0x40);
++ ret |= ds250dfx10_write_register(client, 0x3D, 0x0F, 0x1F);
++
++ // set pre cursor magnitude -4
++ ret |= ds250dfx10_write_register(client, 0x3E, 0x40, 0x40);
++ ret |= ds250dfx10_write_register(client, 0x3E, 0x04, 0x0F);
++
++ // set post cursor magnitude -4
++ ret |= ds250dfx10_write_register(client, 0x3F, 0x40, 0x40);
++ ret |= ds250dfx10_write_register(client, 0x3F, 0x04, 0x0F);
++
++ // deassert cdr
++ ret |= ds250dfx10_write_register(client, 0x0A, 0x00, 0x0C);
++
++ if (!ret)
++ dev_info(&client->dev, "configured channel %u for 1G\n", channel);
++}
++
++static void ds250dfx10_config_10g(struct i2c_client *client, uint8_t channel)
++{
++ int ret = 0;
++
++ // enable smbus access to single channel
++ ret |= ds250dfx10_write_register(client, 0xFF, 0x01, 0x03);
++
++ // select channel
++ ret |= ds250dfx10_write_register(client, 0xFC, 1 << channel, 0xFF);
++
++ // reset channel registers
++ ret |= ds250dfx10_write_register(client, 0x00, 0x04, 0x04);
++
++ // assert cdr
++ ret |= ds250dfx10_write_register(client, 0x0A, 0x0C, 0x0C);
++
++ // disable manual data rate override
++ ret |= ds250dfx10_write_register(client, 0x60, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(client, 0x61, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(client, 0x62, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(client, 0x63, 0x00, 0xFF);
++
++ // set minimum ppm delta tolerance (reset-default)
++ ret |= ds250dfx10_write_register(client, 0x64, 0x00, 0xFF);
++
++ // disable manual divider override
++ ret |= ds250dfx10_write_register(client, 0x09, 0x00, 0x04);
++
++ // select 10.3125 rate
++ ret |= ds250dfx10_write_register(client, 0x2F, 0x00, 0xF0);
++
++ // enable pre- and post-fir
++ ret |= ds250dfx10_write_register(client, 0x3D, 0x80, 0x80);
++
++ // set main cursor magnitude +15
++ ret |= ds250dfx10_write_register(client, 0x3D, 0x00, 0x40);
++ ret |= ds250dfx10_write_register(client, 0x3D, 0x0F, 0x1F);
++
++ // set pre cursor magnitude -4
++ ret |= ds250dfx10_write_register(client, 0x3E, 0x40, 0x40);
++ ret |= ds250dfx10_write_register(client, 0x3E, 0x04, 0x0F);
++
++ // set post cursor magnitude -4
++ ret |= ds250dfx10_write_register(client, 0x3F, 0x40, 0x40);
++ ret |= ds250dfx10_write_register(client, 0x3F, 0x04, 0x0F);
++
++ // deassert cdr
++ ret |= ds250dfx10_write_register(client, 0x0A, 0x00, 0x0C);
++
++ if (!ret)
++ dev_info(&client->dev, "configured channel %u for 10G\n", channel);
++}
++
++static void ds250dfx10_config_25g(struct i2c_client *client, uint8_t channel)
++{
++ int ret = 0;
++
++ // enable smbus access to single channel
++ ret |= ds250dfx10_write_register(client, 0xFF, 0x01, 0x03);
++
++ // select channel
++ ret |= ds250dfx10_write_register(client, 0xFC, 1 << channel, 0xFF);
++
++ // reset channel registers
++ ret |= ds250dfx10_write_register(client, 0x00, 0x04, 0x04);
++
++ // assert cdr
++ ret |= ds250dfx10_write_register(client, 0x0A, 0x0C, 0x0C);
++
++ // disable manual data rate override
++ ret |= ds250dfx10_write_register(client, 0x60, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(client, 0x61, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(client, 0x62, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(client, 0x63, 0x00, 0xFF);
++
++ // set minimum ppm delta tolerance (reset-default)
++ ret |= ds250dfx10_write_register(client, 0x64, 0x00, 0xFF);
++
++ // disable manual divider override
++ ret |= ds250dfx10_write_register(client, 0x09, 0x00, 0x04);
++
++ // select 25.78125 rate
++ ret |= ds250dfx10_write_register(client, 0x2F, 0x50, 0xF0);
++
++ // enable pre- and post-fir
++ ret |= ds250dfx10_write_register(client, 0x3D, 0x80, 0x80);
++
++ // set main cursor magnitude +15
++ ret |= ds250dfx10_write_register(client, 0x3D, 0x00, 0x40);
++ ret |= ds250dfx10_write_register(client, 0x3D, 0x0F, 0x1F);
++
++ // set pre cursor magnitude -4
++ ret |= ds250dfx10_write_register(client, 0x3E, 0x40, 0x40);
++ ret |= ds250dfx10_write_register(client, 0x3E, 0x04, 0x0F);
++
++ // set post cursor magnitude -4
++ ret |= ds250dfx10_write_register(client, 0x3F, 0x40, 0x40);
++ ret |= ds250dfx10_write_register(client, 0x3F, 0x04, 0x0F);
++
++ // deassert cdr
++ ret |= ds250dfx10_write_register(client, 0x0A, 0x00, 0x0C);
++
++ if (!ret)
++ dev_info(&client->dev, "configured channel %u for 25G\n", channel);
++}
++
++static int ds250dfx10_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
++{
++ struct ds250dfx10_phy_priv *priv = phy_get_drvdata(phy);
++
++ if (mode != PHY_MODE_ETHERNET)
++ return -EOPNOTSUPP;
++
++ switch (submode) {
++ case PHY_INTERFACE_MODE_SGMII:
++ ds250dfx10_config_1g(priv->client, priv->channel);
++ break;
++ case PHY_INTERFACE_MODE_10GBASER:
++ ds250dfx10_config_10g(priv->client, priv->channel);
++ break;
++ case PHY_INTERFACE_MODE_25GBASER:
++ ds250dfx10_config_25g(priv->client, priv->channel);
++ break;
++ default:
++ dev_err(&priv->client->dev, "unsupported interface submode %i\n",
++ submode);
++ return -EOPNOTSUPP;
++ }
++
++ return 0;
++}
++
++static const struct phy_ops ds250dfx10_phy_ops = {
++ .set_mode = ds250dfx10_phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static struct phy *ds250dfx10_of_xlate(struct device *dev, struct of_phandle_args *args)
++{
++ struct ds250dfx10_priv *phy_priv = dev_get_drvdata(dev);
++ int channel;
++
++ if (args->args_count != 1) {
++ dev_err(phy_priv->provider->dev, "DT did not pass correct no of args\n");
++ return ERR_PTR(-ENODEV);
++ }
++
++ channel = args->args[0];
++ if (WARN_ON(channel >= ARRAY_SIZE(phy_priv->phy))
++ || !phy_priv->phy[channel])
++ return ERR_PTR(-ENODEV);
++
++ return phy_priv->phy[channel];
++}
++
++static int ds250dfx10_probe(struct i2c_client *client)
++{
++ struct ds250dfx10_priv *priv;
++ struct ds250dfx10_phy_priv *phy_priv;
++ struct device_node *child;
++ uint8_t chan_config_id, device_id, version, chan_version, share_version, channels;
++ uint8_t reg;
++ int ret, i;
++
++ priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv) {
++ ret = -ENOMEM;
++ goto no_phys;
++ }
++ i2c_set_clientdata(client, priv);
++
++ /* read device identification */
++ ret = ds250dfx10_read_register(client, DS250DF410_REG_DEVICE_ID, ®, 0xFF);
++ if (ret)
++ goto no_phys;
++ device_id = reg;
++
++ /* read device version */
++ ret = ds250dfx10_read_register(client, DS250DF410_REG_VERSION, ®, 0xFF);
++ if (ret)
++ goto no_phys;
++ version = reg;
++
++ // report device id
++ dev_info(&client->dev, "device id %#04x version %#04x\n", device_id, version);
++
++ switch (device_id) {
++ case 0x10:
++ break;
++ default:
++ dev_warn(&client->dev, "unknown device id, expect problems!\n");
++ }
++
++ // read channel config id
++ ret = ds250dfx10_read_register(client, DS250DF410_REG_CHAN_CONFIG_ID, ®,
++ DS250DF410_MASK_CHAN_CONFIG_ID);
++ if (ret)
++ goto no_phys;
++ chan_config_id = reg;
++
++ switch (chan_config_id) {
++ case 0xC:
++ channels = 8;
++ break;
++ case 0xE:
++ channels = 4;
++ break;
++ default:
++ dev_err(&client->dev, "unknown channel configuration id %#03x\n", chan_config_id);
++ ret = -EINVAL;
++ goto no_phys;
++ }
++ dev_info(&client->dev, "%u channels\n", channels);
++
++ // read channel version
++ ret = ds250dfx10_read_register(client, DS250DF410_REG_CHAN_VERSION, ®, 0xFF);
++ if (ret)
++ goto no_phys;
++ chan_version = (reg & DS250DF410_MASK_CHAN_VERSION) >> 4;
++ share_version = reg & DS250DF410_MASK_SHARE_VERSION;
++
++ dev_info(&client->dev, "channel version %#03x share version %#03x\n",
++ chan_version, share_version);
++
++ // create PHY objects for all channels
++ for (i = 0; i < channels; i++) {
++ priv->phy[i] = devm_phy_create(&client->dev, child, &ds250dfx10_phy_ops);
++ if (IS_ERR(priv->phy[i])) {
++ ret = PTR_ERR(priv->phy[i]);
++ priv->phy[i] = NULL;
++ of_node_put(child);
++ goto no_provider;
++ }
++
++ phy_priv = devm_kzalloc(&client->dev, sizeof(*phy_priv), GFP_KERNEL);
++ if (!phy_priv) {
++ ret = -ENOMEM;
++ goto no_provider;
++ }
++ phy_set_drvdata(priv->phy[i], phy_priv);
++
++ phy_priv->client = client;
++ phy_priv->channel = i;
++
++ dev_info(&client->dev, "created phy for channel %u\n", i);
++ }
++ of_node_put(child);
++
++ // register self as phy provider with generic lookup function
++ priv->provider = devm_of_phy_provider_register(&client->dev, ds250dfx10_of_xlate);
++
++ return 0;
++
++ devm_of_phy_provider_unregister(&client->dev, priv->provider);
++no_provider:
++ for (i = 0; i < 8; i++) {
++ if (priv->phy[i])
++ devm_phy_destroy(&client->dev, priv->phy[i]);
++ }
++no_phys:
++ return ret;
++}
++
++static void ds250dfx10_remove(struct i2c_client *client)
++{
++ struct ds250dfx10_priv *priv = i2c_get_clientdata(client);
++ int i;
++
++ for (i = 0; i < 8; i++)
++ if (priv->phy[i])
++ devm_phy_destroy(&client->dev, priv->phy[i]);
++}
++
++#ifdef CONFIG_OF
++static const struct of_device_id ds250dfx10_dt_ids[] = {
++ { .compatible = "ti,ds250df410", },
++ { .compatible = "ti,ds250df810", },
++ { }
++};
++MODULE_DEVICE_TABLE(of, ds250dfx10_dt_ids);
++#endif
++
++static struct i2c_device_id ds250dfx10_idtable[] = {
++ { "ds250df410", 0 },
++ { "ds250df810", 1 },
++ { }
++};
++
++MODULE_DEVICE_TABLE(i2c, ds250dfx10_idtable);
++
++static struct i2c_driver ds250dfx10_driver = {
++ .driver = {
++ .name = "ds250dfx10",
++ .of_match_table = of_match_ptr(ds250dfx10_dt_ids),
++ },
++
++ .id_table = ds250dfx10_idtable,
++ .probe = ds250dfx10_probe,
++ .remove = ds250dfx10_remove,
++};
++
++module_i2c_driver(ds250dfx10_driver);
++
++MODULE_AUTHOR("Josua Mayer <josua at solid-run.com>");
++MODULE_DESCRIPTION("TI DS250DFX10 Retimer Driver");
++MODULE_LICENSE("GPL");
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/linux/0011-arm64-dts-lx2162-clearfog-add-description-for-retime.patch b/board/solidrun/lx2160acex7/patches/linux/0011-arm64-dts-lx2162-clearfog-add-description-for-retime.patch
new file mode 100644
index 0000000000..473371e073
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/linux/0011-arm64-dts-lx2162-clearfog-add-description-for-retime.patch
@@ -0,0 +1,52 @@
+From e77c9f9a082b42a765fd2365e6a745007dc49b8f Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sun, 16 Apr 2023 13:24:31 +0300
+Subject: [PATCH 11/13] arm64: dts: lx2162-clearfog: add description for
+ retimer
+
+LX2162 Clearfog has a retimer on 2x SFP+ connectors.
+Add a node for the retimer and link it to the appropriate mac nodes.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ .../boot/dts/freescale/fsl-lx2162a-clearfog.dts | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+index eafef8718a0f..1758e91fdbcf 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+@@ -103,13 +103,15 @@ &dpmac4 {
+ &dpmac5 {
+ sfp = <&sfp_bt>;
+ managed = "in-band-status";
+- phys = <&serdes_1 5>;
++ phys = <&serdes_1 5>, <&retimer 2>, <&retimer 3>;
++ phy-names = "serdes", "retimer", "retimer";
+ };
+
+ &dpmac6 {
+ sfp = <&sfp_bb>;
+ managed = "in-band-status";
+- phys = <&serdes_1 4>;
++ phys = <&serdes_1 4>, <&retimer 0>, <&retimer 1>;
++ phy-names = "serdes", "retimer", "retimer";
+ };
+
+ &dpmac11 {
+@@ -241,7 +243,11 @@ ðernet_phy0 {
+ &i2c2 {
+ status = "okay";
+
+- /* retimer at 18 */
++ retimer: retimer at 18 {
++ compatible = "ti,ds250df410";
++ reg = <0x18>;
++ #phy-cells = <1>;
++ };
+
+ i2c-mux at 70 {
+ compatible = "nxp,pca9546";
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/linux/0012-arm64-dts-lx2160a-clearfog-cx-add-description-for-re.patch b/board/solidrun/lx2160acex7/patches/linux/0012-arm64-dts-lx2160a-clearfog-cx-add-description-for-re.patch
new file mode 100644
index 0000000000..e6ded06d60
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/linux/0012-arm64-dts-lx2160a-clearfog-cx-add-description-for-re.patch
@@ -0,0 +1,81 @@
+From 0ad1b0e326062f8c32f3006d3960f4381fdac61b Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Thu, 31 Oct 2024 15:46:16 +0100
+Subject: [PATCH 12/13] arm64: dts: lx2160a-clearfog-cx: add description for
+ retimers
+
+SolidRun Clearfog-CX (unlike Honeycomb) has QSFP connector driven by
+retimers to support long copper wires.
+
+Add descriptions for both retimers and link them to the relevant
+ethernet interfaces.
+
+Retimers were added with board revision 1.3, earlier baords can use the
+honeycomb dts.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ .../boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 2 +-
+ .../dts/freescale/fsl-lx2160a-clearfog-cx.dts | 36 +++++++++++++++++++
+ 2 files changed, 37 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+index 8f9007ca4941..3fae11353813 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+@@ -112,7 +112,7 @@ regulator at 5c {
+ };
+ };
+
+- i2c at 3 {
++ i2c_smb: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts
+index 86a9b771428d..050d2b565650 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts
+@@ -13,3 +13,39 @@ / {
+ compatible = "solidrun,clearfog-cx",
+ "solidrun,lx2160a-cex7", "fsl,lx2160a";
+ };
++
++&dpmac3 {
++ phys = <&serdes_1 7>, <&retimer0 3>, <&retimer1 3>;
++ phy-names = "serdes", "retimer", "retimer";
++};
++
++&dpmac4 {
++ phys = <&serdes_1 6>, <&retimer0 2>, <&retimer1 2>;
++ phy-names = "serdes", "retimer", "retimer";
++};
++
++&dpmac5 {
++ phys = <&serdes_1 5>, <&retimer0 1>, <&retimer1 1>;
++ phy-names = "serdes", "retimer", "retimer";
++};
++
++&dpmac6 {
++ phys = <&serdes_1 4>, <&retimer0 0>, <&retimer1 0>;
++ phy-names = "serdes", "retimer", "retimer";
++};
++
++&i2c_smb {
++ /* tx direction */
++ retimer0: retimer at 22 {
++ compatible = "ti,ds250df410";
++ reg = <0x22>;
++ #phy-cells = <1>;
++ };
++
++ /* rx direction */
++ retimer1: retimer at 23 {
++ compatible = "ti,ds250df410";
++ reg = <0x23>;
++ #phy-cells = <1>;
++ };
++};
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/linux/0013-arm64-dts-add-description-for-solidrun-lx2160a-cex6-.patch b/board/solidrun/lx2160acex7/patches/linux/0013-arm64-dts-add-description-for-solidrun-lx2160a-cex6-.patch
new file mode 100644
index 0000000000..9b259285f3
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/linux/0013-arm64-dts-add-description-for-solidrun-lx2160a-cex6-.patch
@@ -0,0 +1,568 @@
+From 66979a4cd797926445c19a46fa80c46609b73114 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Fri, 11 Oct 2024 18:21:42 +0200
+Subject: [PATCH 13/13] arm64: dts: add description for solidrun lx2160a cex6
+ evalution board
+
+Add description for the Solid-Run internal CEX Type 6 module and
+evaluation board.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ arch/arm64/boot/dts/freescale/Makefile | 1 +
+ .../dts/freescale/fsl-lx2160a-cex6-evb.dts | 229 ++++++++++++++
+ .../boot/dts/freescale/fsl-lx2160a-cex6.dtsi | 294 ++++++++++++++++++
+ 3 files changed, 524 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6-evb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6.dtsi
+
+diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
+index 59375a2edb5a..e2a7258c4e34 100644
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-bluebox3.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-bluebox3-rev-a.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-cex6-evb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6-evb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6-evb.dts
+new file mode 100644
+index 000000000000..ea6a43a9a5c8
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6-evb.dts
+@@ -0,0 +1,229 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Device Tree file for LX2160A-CEx6 Evaluation Board
++//
++// Copyright 2024 SolidRun Ltd.
++
++/dts-v1/;
++
++#include "fsl-lx2160a.dtsi"
++#include "fsl-lx2160a-cex6.dtsi"
++
++/ {
++ model = "SolidRun LX2160A CEX Type 6 Evaluation Board";
++ compatible = "solidrun,lx2160a-cex6-evb", "solidrun,lx2160a-cex6", "fsl,lx2160a";
++
++ aliases {
++ crypto = &crypto;
++ gpio0 = &gpio0;
++ gpio1 = &gpio1;
++ gpio2 = &gpio2;
++ gpio3 = &gpio3;
++ gpio4 = &expander0;
++ gpio5 = &expander1;
++ gpio6 = &expander2;
++ i2c0 = &i2c0;
++ i2c1 = &i2c2;
++ i2c2 = &i2c3;
++ i2c3 = &i2c_eeprom;
++ i2c4 = &i2c_fan;
++ i2c5 = &i2c_reg;
++ i2c6 = &i2c_mon;
++ i2c7 = &i2c_rtc;
++ i2c8 = &i2c_gpio;
++ i2c9 = &b2b_i2c2;
++ i2c10 = &b2b_i2c3;
++ mmc0 = &esdhc0;
++ mmc1 = &esdhc1;
++ rtc0 = &com_rtc;
++ serial0 = &uart0;
++ serial1 = &uart1;
++ serial2 = &uart2;
++ serial3 = &uart3;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ reg_usb_vbus0: regulator-usb-vbus0 {
++ /*
++ * Power for USB Port 0:
++ * - enable gpio: EC2_RX_DV / GPIO4[23]
++ * - over-current alert gpio (output from regulator): IRQ10 / GPIO3[10]
++ */
++ compatible = "regulator-fixed";
++ regulator-name = "vbus0";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ /* dwc3 driver does not toggle vbus supply */
++ regulator-always-on;
++ };
++
++ reg_usb_vbus1: regulator-usb-vbus1 {
++ /*
++ * Power for USB Port 1:
++ * - enable gpio: EC2_TX_EN / GPIO4[16]
++ * - over-current alert gpio (output from regulator): IRQ11 / GPIO3[11]
++ */
++ compatible = "regulator-fixed";
++ regulator-name = "vbus1";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ /* dwc3 driver does not toggle vbus supply */
++ regulator-always-on;
++ };
++
++ sfp1: sfp-1 { // J67
++ compatible = "sff,sfp";
++ i2c-bus = <&i2c3>;
++ mod-def0-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ sfp2: sfp-2 { // J49
++ compatible = "sff,sfp";
++ i2c-bus = <&i2c2>;
++ mod-def0-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ sfp3: sfp-3 { // J69
++ compatible = "sff,sfp";
++ i2c-bus = <&b2b_i2c2>;
++ mod-def0-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++};
++
++&b2b_i2c3 {
++ /* PCA9655 U10532 @ 20 */
++ expander1: gpio at 20 {
++ compatible = "onnn,pca9655";
++ reg = <0x20>;
++ gpio-controller;
++ gpio-line-names = "GPI0", "GPI1", "GPI2", "GPI3",
++ "IRQ4_N", "IRQ5_N", "USB0_ID", "IRQ0",
++ "GPO0", "GPO1", "GPO2", "GPO3",
++ "WAKE_N2", "WAKE_N1", "USB1_ID", "EN_VBUS1";
++ };
++};
++
++&dpmac4 {
++ sfp = <&sfp2>;
++ managed = "in-band-status";
++ phys = <&serdes_1 6>;
++ status = "okay";
++};
++
++&dpmac5 {
++ sfp = <&sfp1>;
++ managed = "in-band-status";
++ phys = <&serdes_1 5>;
++ status = "okay";
++};
++
++&dpmac6 {
++ sfp = <&sfp3>;
++ managed = "in-band-status";
++ phys = <&serdes_1 4>;
++ status = "okay";
++};
++
++&dspi2 {
++ /* 1x W25Q32FVZPIG (U7) shared by 4 chip-select */
++ spi-num-chipselects = <4>;
++
++ flash at 0 {
++ compatible = "winbond,w25q32", "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <104000000>;
++ m25p,fast-read;
++ };
++
++ flash at 1 {
++ compatible = "winbond,w25q32", "jedec,spi-nor";
++ reg = <1>;
++ spi-max-frequency = <104000000>;
++ m25p,fast-read;
++ };
++
++ flash at 2 {
++ compatible = "winbond,w25q32", "jedec,spi-nor";
++ reg = <2>;
++ spi-max-frequency = <104000000>;
++ m25p,fast-read;
++ };
++
++ flash at 3 {
++ compatible = "winbond,w25q32", "jedec,spi-nor";
++ reg = <3>;
++ spi-max-frequency = <104000000>;
++ m25p,fast-read;
++ };
++};
++
++&fspi {
++ /* flash / xspi extension header @ 1 */
++ spi at 1 {
++ compatible = "rohm,dh2228fv";
++ reg = <1>;
++ /* level shifter on COM may limit speed */
++ spi-max-frequency = <20000000>;
++ };
++};
++
++&i2c0 {
++ /* PCA9655 U10541 @ 21 */
++ expander2: gpio at 21 {
++ compatible = "onnn,pca9655";
++ reg = <0x21>;
++ gpio-controller;
++ gpio-line-names = "TYPE_N0", "TYPE_N1", "TYPE_N2", "TYPE_N3",
++ "THERM_WRN_B_3V3", "IO0_5", "IO0_6", "IO0_7",
++ "IO1_0", "IO1_1", "IO1_2", "IO1_3",
++ "IO1_4", "IO1_5", "IO1_6", "IO1_7";
++ };
++};
++
++&pcie2 {
++ status = "okay";
++};
++
++&pcie3 {
++ status = "okay";
++};
++
++&pcie4 {
++ status = "okay";
++};
++
++&pcie5 {
++ status = "okay";
++};
++
++&pcs_mdio4 {
++ status = "okay";
++};
++
++&pcs_mdio5 {
++ status = "okay";
++};
++
++&pcs_mdio6 {
++ status = "okay";
++};
++
++&usb0 {
++ vbus-supply = <®_usb_vbus0>;
++ status = "okay";
++};
++
++&usb1 {
++ vbus-supply = <®_usb_vbus1>;
++ status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6.dtsi
+new file mode 100644
+index 000000000000..1d97a25bc57f
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex6.dtsi
+@@ -0,0 +1,294 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Device Tree file for LX2160A-CEx6
++//
++// Copyright 2024 SolidRun Ltd.
++
++&crypto {
++ status = "okay";
++};
++
++&dpmac3 {
++ phys = <&serdes_1 7>;
++ phy-names = "serdes";
++ phy-handle = <ðernet_phy1>;
++ phy-connection-type = "10gbase-r";
++ status = "okay";
++};
++
++&dpmac17 {
++ phy-handle = <ðernet_phy0>;
++ phy-connection-type = "rgmii-id";
++ status = "okay";
++};
++
++&emdio1 {
++ status = "okay";
++
++ ethernet_phy0: ethernet-phy at 1 {
++ reg = <1>;
++ qca,smarteee-tw-us-1g = <24>;
++ };
++
++ /* AQR113 PHY */
++ ethernet_phy1: ethernet-phy at 8 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <0x8>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <8 IRQ_TYPE_EDGE_FALLING>; // IRQ08 / GPIO3_DAT08
++ reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; // IIC6_SCL / GPIO1_DAT23
++ };
++};
++
++&dspi2 {
++ status = "okay";
++};
++
++&esdhc0 {
++ no-1-8-v;
++ status = "okay";
++};
++
++&esdhc1 {
++ bus-width = <8>;
++ mmc-hs200-1_8v;
++ mmc-hs400-1_8v;
++ status = "okay";
++};
++
++&fspi {
++ status = "okay";
++
++ flash at 0 {
++ compatible = "micron,mt35xu512aba", "jedec,spi-nor";
++ reg = <0>;
++ m25p,fast-read;
++ spi-max-frequency = <50000000>;
++ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
++ spi-rx-bus-width = <8>;
++ spi-tx-bus-width = <1>;
++ };
++};
++
++&gpio2 {
++ /*
++ * AMC6821 THERM signal uses open-drain logic and can be driven
++ * by either the host (force full-speed) or the chip
++ * (thermal warning). Firmware drives it low during reset.
++ *
++ * Release the signal here for autonomous operation.
++ * TODO: Add support to fan-controller driver.
++ */
++ fan-full-speed-hog {
++ gpio-hog;
++ gpios = <2 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
++ input;
++ line-name = "fan-full-speed";
++ };
++};
++
++&i2c0 {
++ status = "okay";
++
++ i2c-switch at 77 {
++ compatible = "nxp,pca9547";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x77>;
++
++ i2c_eeprom: i2c at 0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++
++ eeprom at 50 {
++ compatible = "atmel,24c512";
++ reg = <0x50>;
++ };
++
++ eeprom at 51 {
++ compatible = "atmel,spd";
++ reg = <0x51>;
++ };
++
++ eeprom at 53 {
++ compatible = "atmel,spd";
++ reg = <0x53>;
++ };
++
++ eeprom at 57 {
++ compatible = "atmel,24c02";
++ reg = <0x57>;
++ };
++ };
++
++ i2c_fan: i2c at 1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++
++ fan-temperature-ctrlr at 18 {
++ compatible = "ti,amc6821";
++ reg = <0x18>;
++ cooling-min-state = <0>;
++ cooling-max-state = <9>;
++ #cooling-cells = <2>;
++ };
++
++ /* fan-controller at 2f (emc2301) */
++
++ /* clock-controller at 6a */
++ };
++
++ i2c_reg: i2c at 2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++
++ regulator at 5c {
++ compatible = "lltc,ltc3882";
++ reg = <0x5c>;
++
++ regulators {
++ /* both outputs are connected, supplying soc core @ 0.8V */
++ vout0 {
++ regulator-name = "VDD_PH1";
++ regulator-always-on;
++ };
++
++ vout1 {
++ regulator-name = "VDD_PH2";
++ regulator-always-on;
++ };
++ };
++ };
++ };
++
++ i2c_mon: i2c at 3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++
++ current-mon at 40 { //GVDD 1.2V
++ compatible = "ti,ina219";
++ reg = <0x40>;
++ shunt-resistor = <1000>;
++ };
++
++ current-mon at 44 { //SD_SVDD 0.9V
++ compatible = "ti,ina219";
++ reg = <0x44>;
++ shunt-resistor = <1000>;
++ };
++
++ current-mon at 42 { //SD_OVDD 1.8V
++ compatible = "ti,ina219";
++ reg = <0x42>;
++ shunt-resistor = <1000>;
++ };
++
++ current-mon at 45 { //OVDD 1.8V
++ compatible = "ti,ina219";
++ reg = <0x45>;
++ shunt-resistor = <1000>;
++ };
++
++ current-mon at 43 { //0.7V AQR113 PHY
++ compatible = "ti,ina219";
++ reg = <0x43>;
++ shunt-resistor = <1000>;
++ };
++
++ current-mon at 46 { //5V
++ compatible = "ti,ina219";
++ reg = <0x46>;
++ shunt-resistor = <1000>;
++ };
++
++ current-mon at 4d { //3.3V
++ compatible = "ti,ina219";
++ reg = <0x4D>;
++ shunt-resistor = <1000>;
++ };
++
++ temp-mon at 4c { // TEMP_DIODE1/2 (U29/U30 - assembly option)
++ compatible = "nxp,sa56004";
++ reg = <0x4c>;
++ #thermal-sensor-cells = <1>;
++ };
++
++ temp-mon at 48 { // temp sensor Q11 (bottom side, edge of pcb, near USD connector)
++ compatible = "nxp,sa56004";
++ reg = <0x48>;
++ #thermal-sensor-cells = <1>;
++ };
++ };
++
++ i2c_rtc: i2c at 4 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <4>;
++
++ com_rtc: rtc at 68 {
++ compatible = "dallas,ds1374";
++ reg = <0x68>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; // IRQ2_RTC_N --> IRQ09 / GPIO3_DAT09
++ };
++ };
++
++ i2c_gpio: i2c at 5 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <5>;
++
++ /* assembly option */
++ expander0: gpio at 41 {
++ compatible = "nxp,pca9536";
++ reg = <0x41>;
++ gpio-controller;
++ gpio-line-names = "USB0_ID", "USB0_VBUS", "USB1_ID", "USB1_VBUS";
++ };
++ };
++
++ b2b_i2c2: i2c at 6 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <6>;
++ };
++
++ b2b_i2c3: i2c at 7 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <7>;
++ };
++ };
++};
++
++&i2c2 {
++ status = "okay";
++};
++
++&i2c3 {
++ status = "okay";
++};
++
++&pcs_mdio3 {
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&uart1 {
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++};
++
++&uart3 {
++ status = "okay";
++};
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0001-lx2162aqds-re-enable-dpmac11.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0001-lx2162aqds-re-enable-dpmac11.patch
new file mode 100644
index 0000000000..7988311628
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0001-lx2162aqds-re-enable-dpmac11.patch
@@ -0,0 +1,27 @@
+From 84fa771a260161361a598eaf77591cf07729557f Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sat, 27 May 2023 17:20:22 +0300
+Subject: [PATCH 01/10] lx2162aqds: re-enable dpmac11
+
+dpmac11 was unintentionally disabled along with dpmac7-10.
+Fix the initializer value of DEVDISR2 to only disable dpmac7-10.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ lx2162aqds/disable_mac7_10.rcw | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/lx2162aqds/disable_mac7_10.rcw b/lx2162aqds/disable_mac7_10.rcw
+index ef3edba..d52589c 100644
+--- a/lx2162aqds/disable_mac7_10.rcw
++++ b/lx2162aqds/disable_mac7_10.rcw
+@@ -11,5 +11,5 @@
+ */
+
+ .pbi
+-write 0x1e00074,0x00007c0
++write 0x1e00074,0x00003c0
+ .end
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0002-add-loadc-jumpc-and-jump-to-pbi-instructions.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0002-add-loadc-jumpc-and-jump-to-pbi-instructions.patch
new file mode 100644
index 0000000000..e8b095d8e9
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0002-add-loadc-jumpc-and-jump-to-pbi-instructions.patch
@@ -0,0 +1,55 @@
+From 8d262bafc2bb4b57ce2331b6eb31d7ad749eaf6c Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh at solid-run.com>
+Date: Mon, 23 Mar 2020 12:16:13 +0200
+Subject: [PATCH 02/10] add loadc, jumpc and jump to pbi instructions
+
+Add 'load conditional', 'jump condidional' and 'jump' to PBI
+instructions.
+
+Signed-off-by: Rabeeh Khoury <rabeeh at solid-run.com>
+---
+ rcw.py | 28 ++++++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/rcw.py b/rcw.py
+index e7d3795..bcd088d 100755
+--- a/rcw.py
++++ b/rcw.py
+@@ -330,6 +330,34 @@ def build_pbi(lines):
+ v2 = struct.pack(endianess + 'L', p2)
+ subsection += v1
+ subsection += v2
++ elif op == 'loadc':
++ if p1 == None or p2 == None:
++ print('Error: "loadc" instruction requires two parameters')
++ return ''
++ v1 = struct.pack(endianess + 'L', 0x80140000)
++ v2 = struct.pack(endianess + 'L', p1)
++ v3 = struct.pack(endianess + 'L', p2)
++ subsection += v1
++ subsection += v2
++ subsection += v3
++ elif op == 'jumpc':
++ if p1 == None or p2 == None:
++ print('Error: "jumpc" instruction requires two parameters')
++ return ''
++ v1 = struct.pack(endianess + 'L', 0x80850000)
++ v2 = struct.pack(endianess + 'L', p1)
++ v3 = struct.pack(endianess + 'L', p2)
++ subsection += v1
++ subsection += v2
++ subsection += v3
++ elif op == 'jump':
++ if p1 == None:
++ print('Error: "jump" instruction requires a parameter')
++ return ''
++ v1 = struct.pack(endianess + 'L', 0x80840000)
++ v2 = struct.pack(endianess + 'L', p1)
++ subsection += v1
++ subsection += v2
+ elif op == 'awrite':
+ if opsize == '.b5':
+ # altconfig write with B=5 (16 bytes)
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0003-lx2160asi-add-bootlocptr-script-for-automatic-boot-f.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0003-lx2160asi-add-bootlocptr-script-for-automatic-boot-f.patch
new file mode 100644
index 0000000000..2aac77c0ee
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0003-lx2160asi-add-bootlocptr-script-for-automatic-boot-f.patch
@@ -0,0 +1,80 @@
+From e6d93b4dfb67a89339527c90ec1c50c2325b025b Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Mon, 7 Oct 2024 14:37:13 +0200
+Subject: [PATCH 03/10] lx2160asi: add bootlocptr script for automatic boot
+ from SD/eMMC/SPI
+
+For each boot source test rcw source, and set bootlocl/h accordingly.
+
+For single boot-source atf create_pbl adds block copy commands
+and sets boot location pointer.
+Automatic boot relies on rcw to include the blockcopy and bootlocptr
+commands, create_pbl then replaces their arguments with actual load
+addresses.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ lx2160asi/bootlocptr_auto.rcw | 51 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 51 insertions(+)
+ create mode 100644 lx2160asi/bootlocptr_auto.rcw
+
+diff --git a/lx2160asi/bootlocptr_auto.rcw b/lx2160asi/bootlocptr_auto.rcw
+new file mode 100644
+index 0000000..08e7916
+--- /dev/null
++++ b/lx2160asi/bootlocptr_auto.rcw
+@@ -0,0 +1,51 @@
++/*
++ * Generic code for auto booting.
++ *
++ * For each boot source test rcw source, and set bootlocl/h accordingly.
++ *
++ * For single boot-source atf create_pbl adds block copy commands
++ * and sets boot location pointer.
++ * Automatic boot relies on rcw to include the blockcopy and bootlocptr
++ * commands, create_pbl then replaces their arguments.
++ *
++ * Copyright 2020 Rabeeh Khoury <rabeeh at solid-run.com>
++ * Copyright 2024 Josua Mayer <josua at solid-run.com>
++ *
++ * Changelog:
++ * - 28/09/2024: changed formatting and comments
++ * - 07/10/2024: removed unnecessary commands to reduce size
++ */
++.pbi
++/* Load condition PORSR1 and mask RCW_SRC */
++loadc 0x01e00000,0x07800000
++
++/* If condition is 0x8 << 23 (SDHC1) then skip the following jump command */
++jumpc 0x00000014,0x04000000
++
++/* skip sdhc1 boot */
++jump 0x20 /* this jump + blockcopy = (4+4+4+4)+(4+4)=24 bytes */
++
++/* copy blocks from sdhc1 (atf create_pbl will fixup arguments) */
++blockcopy 0x08,0x0000a000,0x1800d000,0x00020000
++write 0x01e00400,0x1800d000
++
++/* If condition is 0x9 << 23 (SDHC2) then skip the following jump command */
++jumpc 0x00000014,0x04800000
++
++/* skip sdhc2 boot */
++jump 0x20 /* this jump + blockcopy = (4+4+4+4)+(4+4)=24 bytes */
++
++/* copy blocks from sdhc1 (atf create_pbl will fixup arguments) */
++blockcopy 0x09,0x0000a000,0x1800d000,0x00020000
++write 0x01e00400,0x1800d000
++
++/* If condition is 0xf << 23 (XSPI) then skip the following jump command */
++jumpc 0x00000014,0x07800000
++
++/* skip xspi boot */
++jump 0x20 /* this jump + blockcopy = (4+4+4+4)+(4+4)=24 bytes */
++
++/* copy blocks from xspi (atf create_pbl will fixup arguments) */
++blockcopy 0x0f,0x20009000,0x1800d000,0x00020000
++write 0x01e00400,0x1800d000
++.end
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0004-lx2160asi-add-procedure-splitting-sd1-lanes-A-D-40GE.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0004-lx2160asi-add-procedure-splitting-sd1-lanes-A-D-40GE.patch
new file mode 100644
index 0000000000..d43a30e499
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0004-lx2160asi-add-procedure-splitting-sd1-lanes-A-D-40GE.patch
@@ -0,0 +1,132 @@
+From 2f6d70d10856e7620619af7fa2961cefa68fd2b4 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Wed, 6 Aug 2025 19:14:37 +0200
+Subject: [PATCH 04/10] lx2160asi: add procedure splitting sd1 lanes A-D 40GE.2
+ into 4x10g
+
+Implement custom procedure to reconfigure SD1 protocols 19/20 splitting
+the 40GE.2 port on lanes A-D into 4x XFI.
+
+The procedure is implemented in new rcw file e40g2_split.rcw, following
+the existing e100g1_split.rcw closely.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ lx2160asi/e40g2_split.rcw | 68 +++++++++++++++++++++++++++++++++++++++
+ serdes_28g.rcw | 18 +++++++++++
+ 2 files changed, 86 insertions(+)
+ create mode 100644 lx2160asi/e40g2_split.rcw
+
+diff --git a/lx2160asi/e40g2_split.rcw b/lx2160asi/e40g2_split.rcw
+new file mode 100644
+index 0000000..fa5bb96
+--- /dev/null
++++ b/lx2160asi/e40g2_split.rcw
+@@ -0,0 +1,68 @@
++/*
++ * Split the 40G MAC.2 into 4 x 10G MAC
++ *
++ * NOTICE: The DPC file must be updated as below in order for the MC firmware
++ * to pick up on the change.
++ *
++ * board_info {
++ * serdes {
++ * /* Do not rely on the RCW protocol number, but rather read
++ * * the protocol status registers (PSSR) for each SerDes
++ * * block. That information will be used to enable/disable
++ * * the appropriate MACs.
++ * */
++/* follow_hw_pssr;
++ * };
++ * };
++ */
++#define SRDS_BASE 0x1ea0000 /* SerDes 1 */
++#include <../serdes_28g.rcw>
++
++.pbi
++/* Issue a halt request on all the lanes (A-D) */
++write LNmTRSTCTL(0), T_HLT_REQ(1)
++write LNmRRSTCTL(0), R_HLT_REQ(1)
++
++write LNmTRSTCTL(1), T_HLT_REQ(1)
++write LNmRRSTCTL(1), R_HLT_REQ(1)
++
++write LNmTRSTCTL(2), T_HLT_REQ(1)
++write LNmRRSTCTL(2), R_HLT_REQ(1)
++
++write LNmTRSTCTL(3), T_HLT_REQ(1)
++write LNmRRSTCTL(3), R_HLT_REQ(1)
++
++wait 100
++
++/* Convert Lanes to be configured for 10G. Only the LNmGCR0 needs to be
++ * updated, all other per lane registers are the same between 10G and 40G.
++ */
++write LNmGCR0(0), PORT_RST_LEFT(0) | PORT_LN0_B(0) | PROTO_SEL(0xA) | IF_WIDTH(0x2)
++write LNmGCR0(1), PORT_RST_LEFT(0) | PORT_LN0_B(0) | PROTO_SEL(0xA) | IF_WIDTH(0x2)
++write LNmGCR0(2), PORT_RST_LEFT(0) | PORT_LN0_B(0) | PROTO_SEL(0xA) | IF_WIDTH(0x2)
++write LNmGCR0(3), PORT_RST_LEFT(0) | PORT_LN0_B(0) | PROTO_SEL(0xA) | IF_WIDTH(0x2)
++
++/* Configure the PCC registers */
++/* Only the 40G MAC.1 will remain enabled. PCCE: 0x11000000 -> 0x10000000 */
++write PCCE, E40GA_CFG(1)
++
++/* Enable the 10G protocol converters for XFI. PCCE: 0x00000000 -> 0x00009999 */
++write PCCC, SXGMIIGA_CFG(1) | SXGMIIGB_CFG(1) | SXGMIIGC_CFG(1) | SXGMIIGD_CFG(1) | SXGMIIGA_XFI(1) | SXGMIIGB_XFI(1) | SXGMIIGC_XFI(1) | SXGMIIGD_XFI(1)
++
++/* Issue a reset request on all the lanes (E-H) */
++write LNmTRSTCTL(0), T_RST_REQ(1)
++write LNmRRSTCTL(0), R_RST_REQ(1)
++
++write LNmTRSTCTL(1), T_RST_REQ(1)
++write LNmRRSTCTL(1), R_RST_REQ(1)
++
++write LNmTRSTCTL(2), T_RST_REQ(1)
++write LNmRRSTCTL(2), R_RST_REQ(1)
++
++write LNmTRSTCTL(3), T_RST_REQ(1)
++write LNmRRSTCTL(3), R_RST_REQ(1)
++
++wait 100
++.end
++
++#undef SRDS_BASE
+diff --git a/serdes_28g.rcw b/serdes_28g.rcw
+index e57be41..89de7c3 100644
+--- a/serdes_28g.rcw
++++ b/serdes_28g.rcw
+@@ -59,6 +59,22 @@
+
+ /* PCCD contains the protocol configuration for SXGMII/XFI */
+ #define PCCC (SRDS_BASE + 0x10B0)
++#define SXGMIIGA_XFI(x) (((x) << 31) & 0x80000000)
++#define SXGMIIGB_XFI(x) (((x) << 27) & 0x08000000)
++#define SXGMIIGC_XFI(x) (((x) << 23) & 0x00800000)
++#define SXGMIIGD_XFI(x) (((x) << 19) & 0x00080000)
++#define SXGMIIGE_XFI(x) (((x) << 15) & 0x00008000)
++#define SXGMIIGF_XFI(x) (((x) << 11) & 0x00000800)
++#define SXGMIIGG_XFI(x) (((x) << 7) & 0x00000080)
++#define SXGMIIGH_XFI(x) (((x) << 3) & 0x00000008)
++#define SXGMIIGA_CFG(x) (((x) << 28) & 0x70000000)
++#define SXGMIIGB_CFG(x) (((x) << 24) & 0x07000000)
++#define SXGMIIGC_CFG(x) (((x) << 20) & 0x00700000)
++#define SXGMIIGD_CFG(x) (((x) << 16) & 0x00070000)
++#define SXGMIIGE_CFG(x) (((x) << 12) & 0x00007000)
++#define SXGMIIGF_CFG(x) (((x) << 8) & 0x00000700)
++#define SXGMIIGG_CFG(x) (((x) << 4) & 0x00000070)
++#define SXGMIIGH_CFG(x) ((x) & 0x00000007)
+
+ /* PCCD contains the protocol configuration for E25G */
+ #define PCCD (SRDS_BASE + 0x10B4)
+@@ -75,6 +91,8 @@
+ #define PCCE (SRDS_BASE + 0x10B8)
+ #define E100GB_CFG(x) (((x) << 8) & 0x00000700)
+ #define E100GA_CFG(x) (((x) << 12) & 0x000007000)
++#define E40GB_CFG(x) (((x) << 24) & 0x07000000)
++#define E40GA_CFG(x) (((x) << 28) & 0x070000000)
+
+ #define PEXaCR0(a) (SRDS_BASE + (0x40 * (a)) + 0x1200)
+
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0005-lx2160asi-add-procedure-converting-sd1-lanes-g-h-fro.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0005-lx2160asi-add-procedure-converting-sd1-lanes-g-h-fro.patch
new file mode 100644
index 0000000000..8394c24610
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0005-lx2160asi-add-procedure-converting-sd1-lanes-g-h-fro.patch
@@ -0,0 +1,65 @@
+From cbcd1e26bc5e2c07954fd01e55b3b330d4c7b214 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sun, 24 Aug 2025 14:21:00 +0200
+Subject: [PATCH 05/10] lx2160asi: add procedure converting sd1 lanes g&h from
+ 10g to 25g
+
+Add procedure converting sd1 lanes G and H from 10G to 25G, yielding in
+protocol 18 4x 25G plus 4x 10G ports total.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw | 41 +++++++++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+ create mode 100644 lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw
+
+diff --git a/lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw b/lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw
+new file mode 100644
+index 0000000..40756d8
+--- /dev/null
++++ b/lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw
+@@ -0,0 +1,41 @@
++/* Convert the SD#1 LANE G and H from XFI to 25G */
++#define SRDS_BASE 0x1ea0000 /* SerDes 1 */
++#include <../serdes_28g.rcw>
++
++.pbi
++/* Issue a halt request on the lanes */
++write LNmTRSTCTL(6), T_HLT_REQ(1)
++write LNmRRSTCTL(6), R_HLT_REQ(1)
++write LNmTRSTCTL(7), T_HLT_REQ(1)
++write LNmRRSTCTL(7), R_HLT_REQ(1)
++wait 100
++
++/* Convert lane G from 10G to 25G */
++write LNmGCR0(6), PROTO_SEL(0x1a) | IF_WIDTH(0x4)
++write LNmTGCR0(6), 0x03000000
++write LNmRGCR0(6), 0x03000000
++write LNmRGCR1(6), 0x00000000
++
++/* Convert lane H from 10G to 25G */
++write LNmGCR0(7), PROTO_SEL(0x1a) | IF_WIDTH(0x4)
++write LNmTGCR0(7), 0x03000000
++write LNmRGCR0(7), 0x03000000
++write LNmRGCR1(7), 0x00000000
++
++/* Disable the 10G protocol converters on lanes G and H (enable on A-D, disable E-H) */
++/* TODO: don't change A-D bits? */
++write PCCC, SXGMIIGA_CFG(1) | SXGMIIGB_CFG(1) | SXGMIIGC_CFG(1) | SXGMIIGD_CFG(1) | SXGMIIGA_XFI(1) | SXGMIIGB_XFI(1) | SXGMIIGC_XFI(1) | SXGMIIGD_XFI(1)
++
++/* Enable the 25G protocol converters on lanes G and H (enable on E-H, disable A-D) */
++/* TODO: don't change A-D bits? */
++write PCCD, E25GA_CFG(1) | E25GB_CFG(1) | E25GC_CFG(1) | E25GD_CFG(1)
++
++/* Issue a reset request on the lanes */
++write LNmTRSTCTL(6), T_RST_REQ(1)
++write LNmRRSTCTL(6), R_RST_REQ(1)
++write LNmTRSTCTL(7), T_RST_REQ(1)
++write LNmRRSTCTL(7), R_RST_REQ(1)
++wait 100
++.end
++
++#undef SRDS_BASE
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0006-solidrun-add-script-generating-configs-from-template.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0006-solidrun-add-script-generating-configs-from-template.patch
new file mode 100644
index 0000000000..dfd6dddc5d
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0006-solidrun-add-script-generating-configs-from-template.patch
@@ -0,0 +1,70 @@
+From fe2a405040fe87cd77cb4bf48bd57d0e65777811 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Thu, 7 Nov 2024 13:26:49 +0100
+Subject: [PATCH 06/10] solidrun: add script generating configs from template
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ GenerateSRConfigs.sh | 50 ++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 50 insertions(+)
+ create mode 100755 GenerateSRConfigs.sh
+
+diff --git a/GenerateSRConfigs.sh b/GenerateSRConfigs.sh
+new file mode 100755
+index 0000000..d29471e
+--- /dev/null
++++ b/GenerateSRConfigs.sh
+@@ -0,0 +1,50 @@
++#!/bin/bash -e
++
++generate() {
++ local template=${1}
++ local MODULE=${2}
++ local SOC_REVISION=${3}
++ local BOARD=${4}
++ local CPU_SPEED=${5}
++ local BUS_SPEED=${6}
++ local DDR_SPEED=${7}
++ local SD1=${8}
++ local SD2=${9}
++ local SD3=${10}
++ local BOOTSOURCE=${11}
++
++ local SOC_REVISION_SUFFIX="_rev${SOC_REVISION}"
++ if [ "${SOC_REVISION_SUFFIX}" = "_rev1" ]; then
++ SOC_REVISION_SUFFIX=
++ fi
++
++ local nSD1=${SD1}
++ if [[ $SD1 = *S ]]; then
++ nSD1=${SD1%S}
++ fi
++
++ local nSD2=${SD2}
++ if [[ $SD2 = *S ]]; then
++ nSD2=${SD2%S}
++ fi
++
++ local nSD3=${SD3}
++ if [[ $SD3 = *S ]]; then
++ nSD3=${SD3%S}
++ fi
++
++ local rcw="${MODULE,,}${SOC_REVISION_SUFFIX,,}/${BOARD,,}/rcw_${CPU_SPEED}_${BUS_SPEED}_${DDR_SPEED}_${SD1}_${SD2}_${SD3}_${BOOTSOURCE,,}.rcw"
++ cat "$template" | sed \
++ -e "s;%module%;${MODULE,,};g" -e "s;%MODULE%;${MODULE^^};g" \
++ -e "s;%SOC_REVISION%;${SOC_REVISION};g" \
++ -e "s;%board%;${BOARD,,};g" -e "s;%BOARD%;${BOARD^^};g" \
++ -e "s;%CPU_SPEED%;${CPU_SPEED};g" \
++ -e "s;%BUS_SPEED%;${BUS_SPEED};g" \
++ -e "s;%DDR_SPEED%;${DDR_SPEED};g" \
++ -e "s;%bootsource%;${BOOTSOURCE,,};g" -e "s;%BOOTSOURCE%;${BOOTSOURCE^^};g" \
++ -e "s;%SD1%;${SD1};g" -e "s;%nSD1%;${nSD1};g" \
++ -e "s;%SD2%;${SD2};g" -e "s;%nSD2%;${nSD2};g" \
++ -e "s;%SD3%;${SD3};g" -e "s;%nSD3%;${nSD3};g" \
++ > "$rcw"
++ echo "Generated $rcw"
++}
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0007-add-configuration-solidrun-lx2160a-cex-7-on-clearfog.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0007-add-configuration-solidrun-lx2160a-cex-7-on-clearfog.patch
new file mode 100644
index 0000000000..0a5ccaff43
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0007-add-configuration-solidrun-lx2160a-cex-7-on-clearfog.patch
@@ -0,0 +1,16046 @@
+From 081f7ed231e93d741df55365bcadc9dc699f578e Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Wed, 12 Jun 2024 15:19:39 +0200
+Subject: [PATCH 07/10] add configuration solidrun lx2160a-cex-7 on clearfog-cx
+ board
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ GenerateSRConfigs.sh | 12 +++
+ lx2160acex7/Makefile | 1 +
+ lx2160acex7/README | 0
+ .../rcw_2000_700_2400_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_8_5_2_xspi.rcw | 43 +++++++++
+ lx2160acex7/clearfog-cx/sd1_8_eq.rcwi | 39 ++++++++
+ lx2160acex7/include/SD1_18.rcwi | 24 +++++
+ lx2160acex7/include/SD1_20.rcwi | 24 +++++
+ lx2160acex7/include/SD1_4.rcwi | 25 +++++
+ lx2160acex7/include/SD1_8.rcwi | 24 +++++
+ lx2160acex7/include/SD1_8S.rcwi | 24 +++++
+ lx2160acex7/include/SD2_5.rcwi | 30 ++++++
+ lx2160acex7/include/SD3_2.rcwi | 30 ++++++
+ lx2160acex7/include/bootlocptr.rcwi | 13 +++
+ lx2160acex7/include/common.rcwi | 91 +++++++++++++++++++
+ lx2160acex7/include/common_pbi.rcwi | 57 ++++++++++++
+ lx2160acex7/include/pll_2000_700_xxxx.rcwi | 14 +++
+ lx2160acex7/include/pll_2200_750_xxxx.rcwi | 14 +++
+ lx2160acex7/include/pll_xxxx_xxx_2400.rcwi | 12 +++
+ lx2160acex7/include/pll_xxxx_xxx_2600.rcwi | 12 +++
+ lx2160acex7/include/pll_xxxx_xxx_2666.rcwi | 12 +++
+ lx2160acex7/include/pll_xxxx_xxx_2900.rcwi | 12 +++
+ lx2160acex7/include/pll_xxxx_xxx_3200.rcwi | 12 +++
+ lx2160acex7/include/xspi_limit_17M.rcwi | 12 +++
+ lx2160acex7_clearfog-cx.tmpl | 43 +++++++++
+ lx2160acex7_rev2/Makefile | 1 +
+ lx2160acex7_rev2/README | 0
+ .../rcw_2000_700_2400_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2400_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2600_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2666_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_2900_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2000_700_3200_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2400_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2600_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2666_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_2900_8_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_18_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_18_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_18_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_20_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_20_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_20_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_4_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_4_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_4_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_8S_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_8S_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_8S_5_2_xspi.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_8_5_2_auto.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_8_5_2_sdhc.rcw | 43 +++++++++
+ .../rcw_2200_750_3200_8_5_2_xspi.rcw | 43 +++++++++
+ 325 files changed, 13438 insertions(+)
+ create mode 100644 lx2160acex7/Makefile
+ create mode 100644 lx2160acex7/README
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7/clearfog-cx/sd1_8_eq.rcwi
+ create mode 100644 lx2160acex7/include/SD1_18.rcwi
+ create mode 100644 lx2160acex7/include/SD1_20.rcwi
+ create mode 100644 lx2160acex7/include/SD1_4.rcwi
+ create mode 100644 lx2160acex7/include/SD1_8.rcwi
+ create mode 100644 lx2160acex7/include/SD1_8S.rcwi
+ create mode 100644 lx2160acex7/include/SD2_5.rcwi
+ create mode 100644 lx2160acex7/include/SD3_2.rcwi
+ create mode 100644 lx2160acex7/include/bootlocptr.rcwi
+ create mode 100644 lx2160acex7/include/common.rcwi
+ create mode 100644 lx2160acex7/include/common_pbi.rcwi
+ create mode 100644 lx2160acex7/include/pll_2000_700_xxxx.rcwi
+ create mode 100644 lx2160acex7/include/pll_2200_750_xxxx.rcwi
+ create mode 100644 lx2160acex7/include/pll_xxxx_xxx_2400.rcwi
+ create mode 100644 lx2160acex7/include/pll_xxxx_xxx_2600.rcwi
+ create mode 100644 lx2160acex7/include/pll_xxxx_xxx_2666.rcwi
+ create mode 100644 lx2160acex7/include/pll_xxxx_xxx_2900.rcwi
+ create mode 100644 lx2160acex7/include/pll_xxxx_xxx_3200.rcwi
+ create mode 100644 lx2160acex7/include/xspi_limit_17M.rcwi
+ create mode 100644 lx2160acex7_clearfog-cx.tmpl
+ create mode 100644 lx2160acex7_rev2/Makefile
+ create mode 100644 lx2160acex7_rev2/README
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_20_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_20_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_20_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8S_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8S_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8S_5_2_xspi.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw
+ create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw
+
+diff --git a/GenerateSRConfigs.sh b/GenerateSRConfigs.sh
+index d29471e..aa0ad68 100755
+--- a/GenerateSRConfigs.sh
++++ b/GenerateSRConfigs.sh
+@@ -48,3 +48,15 @@ generate() {
+ > "$rcw"
+ echo "Generated $rcw"
+ }
++
++# generate LX2160A CEX-7 Clearfog-CX
++for DDR_SPEED in 2400 2600 2666 2900 3200; do
++ for SOC_REVISION in 1 2; do
++ for BOOTSOURCE in auto sdhc xspi; do
++ for SD1 in 4 8 8S 18 20; do
++ generate lx2160acex7_clearfog-cx.tmpl lx2160acex7 ${SOC_REVISION} clearfog-cx 2000 700 ${DDR_SPEED} ${SD1} 5 2 ${BOOTSOURCE}
++ generate lx2160acex7_clearfog-cx.tmpl lx2160acex7 ${SOC_REVISION} clearfog-cx 2200 750 ${DDR_SPEED} ${SD1} 5 2 ${BOOTSOURCE}
++ done
++ done
++ done
++done
+diff --git a/lx2160acex7/Makefile b/lx2160acex7/Makefile
+new file mode 100644
+index 0000000..f77e46b
+--- /dev/null
++++ b/lx2160acex7/Makefile
+@@ -0,0 +1 @@
++include ../Makefile.inc
+diff --git a/lx2160acex7/README b/lx2160acex7/README
+new file mode 100644
+index 0000000..e69de29
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..89d7316
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..b98373b
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..0a2a279
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_20_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..9a3cafb
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_20_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..6b2e6ed
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_20_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..aea9e1a
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..7fcd282
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..a0cca33
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..958511e
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8S_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..58916cf
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8S_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..fa28d63
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8S_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..657c1c9
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..d677b0e
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..b8177b5
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..0bf4c7c
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..e98fec5
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..03a8d43
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..98395d4
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_20_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..0e8ceb1
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_20_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..008918c
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_20_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..ac4f9bf
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..3cde581
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..3f3eb6c
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..b5f2d27
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8S_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..3b9bd7b
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8S_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..f971500
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8S_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..e0764ed
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..23a9d00
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..af00ae8
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..9694c69
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..a8974d4
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..3b4b748
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..89d3824
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_20_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..d29e835
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_20_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..29aaeb7
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_20_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..f31fe6b
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..746bbd6
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..ac88ee6
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..2b26668
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8S_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..040134b
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8S_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..9dd5125
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8S_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..433c1bf
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..edfd8b0
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..ee735f2
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..647f8f4
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..0cbcb4c
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..0576a64
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..4ae5145
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_20_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..d76b90f
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_20_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..074fae1
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_20_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..151d6eb
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..ea7bc6a
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..ffbcfab
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..4d74d44
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8S_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..40f8d75
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8S_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..2cc4b66
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8S_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..8c3d356
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..99c689b
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..d79ac32
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..d80a7cd
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..69e0e21
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..07d8d7a
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..c97f328
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_20_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..9a4aade
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_20_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..e463f1f
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_20_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..02f36cd
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..0ca73ab
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..6dd402a
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..5dcddb0
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8S_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..d163475
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8S_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..c703e93
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8S_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..fa5248c
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..866e62f
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..a5eadb3
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..98c7592
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..e97c4c5
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..357adda
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..d4f40bb
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_20_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..3d76099
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_20_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..2b21cba
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_20_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..eff4205
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..c3a820c
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..7512249
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..00351be
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8S_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..ce35428
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8S_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..91ca26f
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8S_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..8f305d1
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..a4905a0
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..c296ce4
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..71f6a0b
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..2007651
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..b7c4d33
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..ae4da60
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_20_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..0773c95
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_20_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..dc9f553
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_20_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..7928984
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..1d7445d
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..2cb6fdc
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..e1d5a9d
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8S_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..e1692e0
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8S_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..41ff280
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8S_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..dd64f8e
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..5b6b24f
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..cf5bf53
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..63e2191
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..ca9e7a2
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..8356dec
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..ce72bb2
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_20_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..dd46ce2
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_20_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..404725d
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_20_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..6dc4678
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..4204c51
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..ca4a71d
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..2365d7b
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8S_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..5aedd6d
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8S_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..da3c4b3
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8S_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..33c946c
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..aad4aa0
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..f1eb1d2
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..4330d69
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..7133744
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..e5e8607
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..e8018ce
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_20_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..de03a16
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_20_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..2339c62
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_20_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..a189b51
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..90a88c9
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..e0d5d2c
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..6b38fd0
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8S_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..6b43562
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8S_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..a7291df
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8S_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..8a2a898
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..d70f8f2
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..7404658
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..aabbf82
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..29e7fe1
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..3552047
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..19213cd
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_20_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..876a1be
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_20_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..62630a9
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_20_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..2d551e3
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..cbf42f1
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..47b7318
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..7625db7
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8S_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..c6606d2
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8S_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..62c6eee
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8S_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..7fa4957
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..9829eba
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..a600b7a
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..08c7d45
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 1.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 1
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7/clearfog-cx/sd1_8_eq.rcwi b/lx2160acex7/clearfog-cx/sd1_8_eq.rcwi
+new file mode 100644
+index 0000000..44961c1
+--- /dev/null
++++ b/lx2160acex7/clearfog-cx/sd1_8_eq.rcwi
+@@ -0,0 +1,39 @@
++/*
++ * SERDES tuning based on the following hardware -
++ * - SolidRun COM express type 7 revision 1.7 and newer
++ * - SolidRun ClearFog CX revision 1.3 with TI retimers and EPT COM express headers
++ */
++
++.pbi
++/* Lane E (SD1 TX/RX 3) */
++write 0x01EA0C28,0x00000000
++write 0x01EA0C30,0x20818120
++write 0x01EA0C34,0x23000000
++write 0x01EA0C68,0x80000000
++write 0x01EA0C74,0x00002020
++write 0x01EA0C80,0x00008000
++
++/* Lane F (SD1 TX/RX 2)*/
++write 0x01EA0D28,0x00000000
++write 0x01EA0D30,0x20818120
++write 0x01EA0D34,0x23000000
++write 0x01EA0D68,0x80000000
++write 0x01EA0D74,0x00002020
++write 0x01EA0D80,0x00008000
++
++/* Lane G (SD1 TX/RX 1)*/
++write 0x01EA0E28,0x00000000
++write 0x01EA0E30,0x20818120
++write 0x01EA0E34,0x23000000
++write 0x01EA0E68,0x80000000
++write 0x01EA0E74,0x00002020
++write 0x01EA0E80,0x00008000
++
++/* Lane H (SD1 TX/RX 0)*/
++write 0x01EA0F28,0x00000000
++write 0x01EA0F30,0x20818120
++write 0x01EA0F34,0x23000000
++write 0x01EA0F68,0x80000000
++write 0x01EA0F74,0x00002020
++write 0x01EA0F80,0x00008000
++.end
+diff --git a/lx2160acex7/include/SD1_18.rcwi b/lx2160acex7/include/SD1_18.rcwi
+new file mode 100644
+index 0000000..cf67395
+--- /dev/null
++++ b/lx2160acex7/include/SD1_18.rcwi
+@@ -0,0 +1,24 @@
++/*
++ * Serdes 1 Reference Clocks:
++ * - PLLF = 161.1328125MHz
++ * - PLLS = 100MHz
++ */
++
++/* Serdes 1 Protocol 18: 6x10Gbps + 2x25Gbps */
++SRDS_PRTCL_S1=18
++
++/* Enable PLLF */
++SRDS_PLL_PD_PLL1=0
++
++/* Use PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S1=1
++
++/* Enable PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/*
++ * Select PLLF frequency 161.1328125MH for 25G mode: Bit 0 = 0
++ * Select PLLS frequency 161.1328125MHz for 10G mode: Bit 1 = 1
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=2
+diff --git a/lx2160acex7/include/SD1_20.rcwi b/lx2160acex7/include/SD1_20.rcwi
+new file mode 100644
+index 0000000..f5c0c66
+--- /dev/null
++++ b/lx2160acex7/include/SD1_20.rcwi
+@@ -0,0 +1,24 @@
++/*
++ * Serdes 1 Reference Clocks:
++ * - PLLF = 161.1328125MHz
++ * - PLLS = 100MHz
++ */
++
++/* Serdes 1 Protocol 20: 2x40Gbps */
++SRDS_PRTCL_S1=20
++
++/* Disable PLLF */
++SRDS_PLL_PD_PLL1=1
++
++/* Use PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S1=1
++
++/* Enable PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/*
++ * Select PLLF frequency 156.25MHz for 10G mode: Bit 0 = 0 (don't care)
++ * Select PLLS frequency 161.1328125MHz for 10G mode: Bit 1 = 1
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=2
+diff --git a/lx2160acex7/include/SD1_4.rcwi b/lx2160acex7/include/SD1_4.rcwi
+new file mode 100644
+index 0000000..3c6023a
+--- /dev/null
++++ b/lx2160acex7/include/SD1_4.rcwi
+@@ -0,0 +1,25 @@
++/*
++ * Serdes 1 Reference Clocks:
++ * - PLLF = 161.1328125MHz
++ * - PLLS = 100MHz
++ */
++
++/* Serdes 1 Protocol 4: 8x1Gbps */
++SRDS_PRTCL_S1=4
++
++/* Disable PLLF */
++SRDS_PLL_PD_PLL1=1
++SRDS_REFCLKF_DIS_S1=1
++
++/* Don't use PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S1=0
++
++/* Enable PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/*
++ * Select PLLF frequency 100MHz (don't care): Bit 0 = 0
++ * Select PLLS frequency 100MHz: Bit 1 = 0
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=0
+diff --git a/lx2160acex7/include/SD1_8.rcwi b/lx2160acex7/include/SD1_8.rcwi
+new file mode 100644
+index 0000000..1646de8
+--- /dev/null
++++ b/lx2160acex7/include/SD1_8.rcwi
+@@ -0,0 +1,24 @@
++/*
++ * Serdes 1 Reference Clocks:
++ * - PLLF = 161.1328125MHz
++ * - PLLS = 100MHz
++ */
++
++/* Serdes 1 Protocol 8: 8x10Gbps */
++SRDS_PRTCL_S1=8
++
++/* Disable PLLF */
++SRDS_PLL_PD_PLL1=1
++
++/* Use PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S1=1
++
++/* Enable PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/*
++ * Select PLLF frequency 100MHz (don't care): Bit 0 = 0
++ * Select PLLS frequency 161.1328125MHz: Bit 1 = 1
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=2
+diff --git a/lx2160acex7/include/SD1_8S.rcwi b/lx2160acex7/include/SD1_8S.rcwi
+new file mode 100644
+index 0000000..c043eef
+--- /dev/null
++++ b/lx2160acex7/include/SD1_8S.rcwi
+@@ -0,0 +1,24 @@
++/*
++ * Serdes 1 Reference Clocks:
++ * - PLLF = 100MHz
++ * - PLLS = 161.1328125MHz
++ */
++
++/* Serdes 1 Protocol 8: 8x10Gbps */
++SRDS_PRTCL_S1=8
++
++/* Enable PLLF (to support sgmii protocol switch) */
++SRDS_PLL_PD_PLL1=0
++
++/* Don't use PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S1=0
++
++/* Enable PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/*
++ * Select PLLF frequency 100MHz (to support sgmii protocol switch): Bit 0 = 0
++ * Select PLLS frequency 161.1328125MHz: Bit 1 = 1
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=2
+diff --git a/lx2160acex7/include/SD2_5.rcwi b/lx2160acex7/include/SD2_5.rcwi
+new file mode 100644
+index 0000000..c01ed1f
+--- /dev/null
++++ b/lx2160acex7/include/SD2_5.rcwi
+@@ -0,0 +1,30 @@
++/*
++ * Serdes 2 Reference Clocks:
++ * - PLLF = 100MHz
++ * - PLLS = 100MHz
++ */
++
++/* Serdes 2 Protocol 5: 1x PCI-e x4 Gen 3 + 4x SATA */
++SRDS_PRTCL_S2=5
++
++/* Enable PLLF */
++SRDS_PLL_PD_PLL3=0
++
++/* Don't use PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S2=0
++
++/* Enable PLLS */
++SRDS_PLL_PD_PLL4=0
++
++/*
++ * Select PLLF frequency 100MHz: Bit 0 = 0
++ * Select PLLS frequency 100MHz: Bit 1 = 0
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935)
++ */
++SRDS_PLL_REF_CLK_SEL_S2=0
++
++/* Support up to PCI-e Gen 3 */
++SRDS_DIV_PEX_S2=1
++
++/* indicate PCI ports for pbi section errata application*/
++#define HAVE_PEX3
+diff --git a/lx2160acex7/include/SD3_2.rcwi b/lx2160acex7/include/SD3_2.rcwi
+new file mode 100644
+index 0000000..630b0b2
+--- /dev/null
++++ b/lx2160acex7/include/SD3_2.rcwi
+@@ -0,0 +1,30 @@
++/*
++ * Serdes 3 Reference Clocks:
++ * - PLLF = 100MHz
++ * - PLLS = 100MHz
++ */
++
++/* Serdes 3 Protocol 2: 1x PCI-e x8 Gen 3 */
++SRDS_PRTCL_S3=2
++
++/* Disable PLLF */
++SRDS_PLL_PD_PLL5=1
++
++/* Don't use Serdes 3 PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S3=0
++
++/* Enable PLLS */
++SRDS_PLL_PD_PLL6=0
++
++/*
++ * Select PLLF frequency 100MHz: Bit 0 = 0
++ * Select PLLS frequency 100MHz: Bit 1 = 0
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 936-937)
++ */
++SRDS_PLL_REF_CLK_SEL_S3=0
++
++/* Support up to PCI-e Gen 3 */
++SRDS_DIV_PEX_S3=1
++
++/* indicate PCI ports for pbi section errata application*/
++#define HAVE_PEX5
+diff --git a/lx2160acex7/include/bootlocptr.rcwi b/lx2160acex7/include/bootlocptr.rcwi
+new file mode 100644
+index 0000000..4bbfc5c
+--- /dev/null
++++ b/lx2160acex7/include/bootlocptr.rcwi
+@@ -0,0 +1,13 @@
++#if defined(LX_BOOTSOURCE_AUTO)
++/*
++ * For automatic boot-media selection ATF patches blockcopy and bootlocptr
++ * instructions in-place for all 3 supported boot media.
++ * Add the necessary jump instructions and placeholders.
++ */
++#include <../lx2160asi/bootlocptr_auto.rcw>
++#else
++/*
++ * ATF create_pbl will automatically append bootlocptr instructions,
++ * no need to include ../lx2160asi/bootlocptr_{nor,sd}.rcw
++ */
++#endif
+diff --git a/lx2160acex7/include/common.rcwi b/lx2160acex7/include/common.rcwi
+new file mode 100644
+index 0000000..c76b174
+--- /dev/null
++++ b/lx2160acex7/include/common.rcwi
+@@ -0,0 +1,91 @@
++/*
++ * LX2160A COM-Express Type 7 Common Configuration
++ */
++
++/* C[5:8]_PLL are CG[5:8] div 1 */
++C5_PLL_SEL=0
++C6_PLL_SEL=0
++C7_PLL_SEL=0
++C8_PLL_SEL=0
++/* Cluster group A clock is PLL1 div 1 (unused on LX2160A) */
++HWA_CGA_M1_CLK_SEL=1
++/* Cluster group B clock is PLL2 div 2 (for DCE) */
++HWA_CGB_M1_CLK_SEL=6
++/*
++ * fall-back boot-mode when DCFG boot location pointer registers are null
++ * - 0b10101 (21): OCRAM
++ * - 0b11010 (26): XSPI
++ */
++BOOT_LOC=21
++/* SYSCLK is 100MHz */
++SYSCLK_FREQ=600
++/* USB-3.0 clock is 100MHz */
++USB3_CLK_FSEL=39
++
++/* IIC1 is I2C */
++IIC1_PMUX=0
++/* IIC2 is SD Card-Detect */
++IIC2_PMUX=6
++/* IIC3 is I2C */
++IIC3_PMUX=0
++/* IIC4 is I2C (unused) */
++IIC4_PMUX=0
++/* IIC5 is I2C */
++IIC5_PMUX=0
++/* IIC6 is I2C (unused) */
++IIC6_PMUX=0
++/*
++ * SDHC1 CMD/CLK/VBUS/DAT[0:3] are SDHC
++ * SPI3_PCS0 is VSEL
++ */
++SDHC1_BASE_PMUX=0
++/* SDHC1_DS is GPIO (unused) */
++SDHC1_DS_PMUX=1
++/* SDHC1_CMD/DAT0/DAT1_DIR (SPI3_PCS[1:3]) are GPIO1[14:12] */
++SDHC1_DIR_PMUX=1
++/* USB[1:2]_DRVVBUS/PWRFAULT are GPIO4[28:25] (unused) */
++USB_EXT_PMUX=1
++/* XSPI1_A_DQS/SCK/CS0_B/CS1_B are SPI */
++XSPI1_A_BASE_PMUX=0
++/* XSPI1_A_DATA[3:0] are SPI */
++XSPI1_A_DATA30_PMUX=0
++/* XSPI1_A_DATA[7:4] are SPI */
++XSPI1_A_DATA74_PMUX=0
++/* ASLEEP is ASLEEP (unused) */
++ASLEEP_PMUX=0
++/* EVT[2:0] are GPIO3[14:12] */
++EVT20_PMUX=1
++/* EVT[4:3] are GPIO3[16:15] */
++EVT43_PMUX=1
++/* CLK_OUT is GPIO (unused) */
++CLK_OUT_PMUX=1
++/* IRQ[3:0] are GPIO3[3:0] */
++IRQ03_00_PMUX=1
++/* IRQ[7:4] are GPIO3[7:4] */
++IRQ07_04_PMUX=1
++/* IRQ[11:8] are GPIO3[11:8] */
++IRQ11_08_PMUX=1
++/* EC1_* are RGMII */
++EC1_PMUX=0
++/* EC2_* are PTP */
++EC2_PMUX=2
++/* EC_GTX_CLK125 is PTP */
++GTX_CLK_PMUX=0
++/* UART1_SOUT/SIN are UART1 */
++UART1_SOUTSIN_PMUX=0
++/* UART1_RTS/CTS_B are GPIO (unused) */
++UART1_RTSCTS_PMUX=1
++/* UART2_SOUT/SIN are UART2 */
++UART2_SOUTSIN_PMUX=0
++/* UART2_RTS/CTS_B are GPIO (unused) */
++UART2_RTSCTS_PMUX=1
++/* SDHC2_CMD/DAT[3:0]/DS/CLK are SDHC */
++SDHC2_BASE_PMUX=0
++/* SDHC2_DAT[7:4] are SDHC */
++SDHC2_DAT74_PMUX=0
++
++/*
++ * Original SolidRun Settings in LSDK-21.08
++ *
++ * HWA_CGB_M1_CLK_SEL=7 // Cluster Group B PLL 2 / 3 is clock
++ */
+diff --git a/lx2160acex7/include/common_pbi.rcwi b/lx2160acex7/include/common_pbi.rcwi
+new file mode 100644
+index 0000000..13c60b9
+--- /dev/null
++++ b/lx2160acex7/include/common_pbi.rcwi
+@@ -0,0 +1,57 @@
++/*
++ * LX2160A COM-Express Type 7 Common Configuration
++ */
++
++/* Drive the fan full speed pin */
++.pbi
++write 0x2320000,0x20000000
++.end
++
++/* Errata to write on scratch reg for validation */
++#include <../lx2160asi/scratchrw1.rcw>
++
++/* Errata for SATA controller */
++#include <../lx2160asi/a010554.rcw>
++
++#if LX_SR == 1
++/* Errata for PCIe controller */
++#include <../lx2160asi/a011270.rcw>
++#include <../lx2160asi/a050234.rcw>
++#endif
++
++/* common PBI commands */
++#include <../lx2160asi/common.rcw>
++
++#if LX_SR == 2
++/* PCIe Errata A-009531, A-008851 */
++#ifdef HAVE_PEX1
++#include <../lx2160asi/a009531_PEX1.rcw>
++#include <../lx2160asi/a008851_PEX1.rcw>
++#endif /* HAVE_PEX1 */
++#ifdef HAVE_PEX2
++#include <../lx2160asi/a009531_PEX2.rcw>
++#include <../lx2160asi/a008851_PEX2.rcw>
++#endif /* HAVE_PEX2 */
++#ifdef HAVE_PEX3
++#include <../lx2160asi/a009531_PEX3.rcw>
++#include <../lx2160asi/a008851_PEX3.rcw>
++#endif /* HAVE_PEX3 */
++#ifdef HAVE_PEX4
++#include <../lx2160asi/a009531_PEX4.rcw>
++#include <../lx2160asi/a008851_PEX4.rcw>
++#endif /* HAVE_PEX4 */
++#ifdef HAVE_PEX5
++#include <../lx2160asi/a009531_PEX5.rcw>
++#include <../lx2160asi/a008851_PEX5.rcw>
++#endif /* HAVE_PEX5 */
++#ifdef HAVE_PEX6
++#include <../lx2160asi/a009531_PEX6.rcw>
++#include <../lx2160asi/a008851_PEX6.rcw>
++#endif /* HAVE_PEX6 */
++
++/*SerDes Errata A-050479*/
++#include <../lx2160asi/a050479.rcw>
++#endif
++
++/* Errata A-050426 */
++#include <../lx2160asi/a050426.rcw>
+diff --git a/lx2160acex7/include/pll_2000_700_xxxx.rcwi b/lx2160acex7/include/pll_2000_700_xxxx.rcwi
+new file mode 100644
+index 0000000..2a3725f
+--- /dev/null
++++ b/lx2160acex7/include/pll_2000_700_xxxx.rcwi
+@@ -0,0 +1,14 @@
++/*
++ * Core and Platform Clocks:
++ * - Platform: 700MHz
++ * - Core: 2000MHz
++ */
++
++/* platform clock is system clock mul 14 div 2 = 700 */
++SYS_PLL_RAT=14
++
++/* core clocks are 2000 */
++CGA_PLL1_RAT=20
++CGA_PLL2_RAT=20
++CGB_PLL1_RAT=20
++CGB_PLL2_RAT=7
+diff --git a/lx2160acex7/include/pll_2200_750_xxxx.rcwi b/lx2160acex7/include/pll_2200_750_xxxx.rcwi
+new file mode 100644
+index 0000000..0f57b67
+--- /dev/null
++++ b/lx2160acex7/include/pll_2200_750_xxxx.rcwi
+@@ -0,0 +1,14 @@
++/*
++ * Core and Platform Clocks:
++ * - Platform: 750MHz
++ * - Core: 2200MHz
++ */
++
++/* platform clock is system clock mul 15 div 2 = 750 */
++SYS_PLL_RAT=15
++
++/* core clocks are 2200 */
++CGA_PLL1_RAT=22
++CGA_PLL2_RAT=22
++CGB_PLL1_RAT=22
++CGB_PLL2_RAT=7
+diff --git a/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi
+new file mode 100644
+index 0000000..6356b36
+--- /dev/null
++++ b/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi
+@@ -0,0 +1,12 @@
++/*
++ * DDR Rate: 2400MHz
++ *
++ * DDR PHY Clock (half ddr clock, quarter mts rate)
++ * multiplier = 24 (24)
++ * divider = 4 (3)
++ * 100MHz x 24 / 4 = 600MHz (MTS = 4 x 600 = 2400MHz)
++ */
++MEM_PLL_RAT=24
++MEM_PLL_CFG=3
++MEM2_PLL_RAT=24
++MEM2_PLL_CFG=3
+diff --git a/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi
+new file mode 100644
+index 0000000..d72047d
+--- /dev/null
++++ b/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi
+@@ -0,0 +1,12 @@
++/*
++ * DDR Rate: 2600MHz
++ *
++ * DDR PHY Clock (half ddr clock, quarter mts rate)
++ * multiplier = 26 (26)
++ * divider = 4 (3)
++ * 100MHz x 26 / 4 = 650MHz (MTS = 4 x 650 = 2600MHz)
++ */
++MEM_PLL_RAT=26
++MEM_PLL_CFG=3
++MEM2_PLL_RAT=26
++MEM2_PLL_CFG=3
+diff --git a/lx2160acex7/include/pll_xxxx_xxx_2666.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2666.rcwi
+new file mode 100644
+index 0000000..06d3da1
+--- /dev/null
++++ b/lx2160acex7/include/pll_xxxx_xxx_2666.rcwi
+@@ -0,0 +1,12 @@
++/*
++ * DDR Rate: 2666MHz
++ *
++ * DDR PHY Clock (half ddr clock, quarter mts rate)
++ * multiplier = 20 (20)
++ * divider = 3 (2)
++ * 100MHz x 20 / 3 = 666MHz (MTS = 4 x 666 = 2666MHz)
++ */
++MEM_PLL_RAT=20
++MEM_PLL_CFG=2
++MEM2_PLL_RAT=20
++MEM2_PLL_CFG=2
+diff --git a/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi
+new file mode 100644
+index 0000000..9ad274f
+--- /dev/null
++++ b/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi
+@@ -0,0 +1,12 @@
++/*
++ * DDR Rate: 2900MHz
++ *
++ * DDR PHY Clock (half ddr clock, quarter mts rate)
++ * multiplier = 29 (29)
++ * divider = 4 (3)
++ * 100MHz x 29 / 4 = 725MHz (MTS = 4 x 725 = 2900MHz)
++ */
++MEM_PLL_RAT=29
++MEM_PLL_CFG=3
++MEM2_PLL_RAT=29
++MEM2_PLL_CFG=3
+diff --git a/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi b/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi
+new file mode 100644
+index 0000000..abf7e9d
+--- /dev/null
++++ b/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi
+@@ -0,0 +1,12 @@
++/*
++ * DDR Rate: 3200MHz
++ *
++ * DDR PHY Clock (half ddr clock, quarter mts rate)
++ * multiplier = 32 (32)
++ * divider = 4 (3)
++ * 100MHz x 32 / 4 = 800MHz (MTS = 4 x 800 = 3200MHz)
++ */
++MEM_PLL_RAT=32
++MEM_PLL_CFG=3
++MEM2_PLL_RAT=32
++MEM2_PLL_CFG=3
+diff --git a/lx2160acex7/include/xspi_limit_17M.rcwi b/lx2160acex7/include/xspi_limit_17M.rcwi
+new file mode 100644
+index 0000000..0de9191
+--- /dev/null
++++ b/lx2160acex7/include/xspi_limit_17M.rcwi
+@@ -0,0 +1,12 @@
++/*
++ * FlexSPI controller supports modifcation of the FlexSPI Clock
++ * divisor value, default value of this is 80.
++ * For 700 MHz, FlexSPI clock runs with default value is
++ * (Platform Clock * 2) / (Divisor value)
++ * => 700 * 2 / 80 ==> 17MHz
++ * On Clearfog-CX bus speed is limited to 20MHz by a mux on carrier board.
++ * Explicitly set the default value again, in case it was modified elsewhere.
++ */
++.pbi
++write 0x1e00900,0x00000014
++.end
+diff --git a/lx2160acex7_clearfog-cx.tmpl b/lx2160acex7_clearfog-cx.tmpl
+new file mode 100644
+index 0000000..a651132
+--- /dev/null
++++ b/lx2160acex7_clearfog-cx.tmpl
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - %SD1%
++ * SerDes Protocol 2 - %SD2%
++ * SerDes Protocol 3 - %SD3%
++ *
++ * Frequencies:
++ * Core -- %CPU_SPEED% MHz
++ * Platform -- %BUS_SPEED% MHz
++ * DDR -- %DDR_SPEED% MT/s
++ *
++ * Silicon %SOC_REVISION%.0
++ * Boot from %BOOTSOURCE%
++ */
++
++#define LX_SR %SOC_REVISION%
++#define LX_BOOTSOURCE_%BOOTSOURCE%
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../%module%/include/pll_%CPU_SPEED%_%BUS_SPEED%_xxxx.rcwi>
++#include <../%module%/include/pll_xxxx_xxx_%DDR_SPEED%.rcwi>
++#include <../%module%/include/common.rcwi>
++#include <../%module%/include/SD1_%SD1%.rcwi>
++#include <../%module%/include/SD2_%SD2%.rcwi>
++#include <../%module%/include/SD3_%SD3%.rcwi>
++#include <../%module%/include/common_pbi.rcwi>
++#include <../%module%/include/xspi_limit_17M.rcwi>
++#include <../%module%/include/bootlocptr.rcwi>
++
++#if %nSD1% == 18 || %nSD1% == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if %nSD1% == 20 || %nSD1% == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/Makefile b/lx2160acex7_rev2/Makefile
+new file mode 100644
+index 0000000..f77e46b
+--- /dev/null
++++ b/lx2160acex7_rev2/Makefile
+@@ -0,0 +1 @@
++include ../Makefile.inc
+diff --git a/lx2160acex7_rev2/README b/lx2160acex7_rev2/README
+new file mode 100644
+index 0000000..e69de29
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..c5ca0e4
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..f861d85
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..7dd1f39
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_20_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..514608f
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_20_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..7d9b8ad
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_20_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..0f2575c
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..08698a5
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..bbdcd43
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..b85f5ce
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8S_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..f14047e
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8S_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..58f5d7f
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8S_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..45fd619
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..7f743a7
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..1cdcb4b
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..ee2fc9d
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..7a19e4c
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..bc78d81
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..5d75610
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_20_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..5a0aba8
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_20_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..de890e9
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_20_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..c10550d
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..c558725
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..6fa582d
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..7e0663a
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8S_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..63872c6
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8S_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..a07e2ff
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8S_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..0206ab8
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..eca5bdc
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..ba8bd15
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..412a5af
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..23ce88d
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..ac59ba9
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..a8e08ab
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_20_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..ae9f374
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_20_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..eb19a73
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_20_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..0b9dbcb
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..5fff512
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..472b313
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..fa4e599
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8S_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..86e0a8d
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8S_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..1db4d38
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8S_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..3a8710f
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..c444ba0
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..9d4a038
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..a79c43b
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..3018c0f
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..da04125
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..2b1d335
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_20_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..65a4fcf
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_20_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..d56b661
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_20_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..0a3d08a
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..ca78e2e
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..85fa663
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..f13fc52
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8S_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..833ac5f
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8S_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..b6f6c2f
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8S_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..cc99361
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..02f6fe6
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..6f63d22
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..81a43ef
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..8a94368
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..145914a
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..db57819
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_20_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..7b93de2
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_20_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..7e113a0
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_20_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..b855e5e
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..5c7fcf5
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..8aee73c
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..34eb250
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8S_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..e3f5c4d
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8S_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..cc7a064
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8S_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..bf8d789
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..65b19b0
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..cb4a102
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..34993f6
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..736d632
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..9de5f31
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..202b672
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_20_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..1596f52
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_20_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..b212b18
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_20_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..12f9532
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..348f5fe
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..1f8ec0c
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..745343e
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8S_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..3a2e565
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8S_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..048553f
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8S_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..651322b
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..0923a67
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..1bf8607
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..dbcc16b
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..536dfe2
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..2f55dad
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..fe04667
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_20_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..26d16ab
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_20_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..22e2543
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_20_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..4fddc2f
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..d363819
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..2b4858e
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..20ee963
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8S_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..9b6fc4e
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8S_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..a2794e3
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8S_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..f27718e
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..f9fcf83
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..13a4b9d
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..7a6579f
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..64704a4
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..d4a2c14
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..9d5ad49
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_20_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..f5b5973
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_20_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..218df8e
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_20_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..6448483
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..9f166e3
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..bfef455
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..3efef71
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8S_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..87e8453
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8S_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..7ee736f
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8S_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..de4b48b
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..54aad1f
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..c045c66
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..b62a08b
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..5ee1010
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..8187d1d
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..afd1e15
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_20_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..11004c1
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_20_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..24aed43
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_20_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..b5b81c0
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..fe8e4d1
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..fdb5257
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..e1f3265
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8S_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..475d72d
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8S_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..705e5f2
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8S_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..240d4eb
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..a9ae2de
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..eeaadfd
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..d02fe60
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw
+new file mode 100644
+index 0000000..f1b70f0
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..94556ff
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw
+new file mode 100644
+index 0000000..a185a34
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_18_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_18.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 18 == 20 || 18 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_20_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_20_5_2_auto.rcw
+new file mode 100644
+index 0000000..2cf4d60
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_20_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_20_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_20_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..791082b
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_20_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_20_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_20_5_2_xspi.rcw
+new file mode 100644
+index 0000000..cd1a268
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_20_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 20
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_20.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 20 == 18 || 20 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 20 == 20 || 20 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw
+new file mode 100644
+index 0000000..bfd8171
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..6ba0ca8
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw
+new file mode 100644
+index 0000000..1cb0194
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_4_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 4
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_4.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 4 == 18 || 4 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 4 == 20 || 4 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8S_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8S_5_2_auto.rcw
+new file mode 100644
+index 0000000..856d088
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8S_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8S_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8S_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..d1652af
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8S_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8S_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8S_5_2_xspi.rcw
+new file mode 100644
+index 0000000..5ed8f21
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8S_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw
+new file mode 100644
+index 0000000..256f3cf
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw
+new file mode 100644
+index 0000000..7b82d9c
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from SDHC
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_SDHC
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw
+new file mode 100644
+index 0000000..6945f23
+--- /dev/null
++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw
+@@ -0,0 +1,43 @@
++/*
++ * SerDes Protocol 1 - 8
++ * SerDes Protocol 2 - 5
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from XSPI
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_XSPI
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8.rcwi>
++#include <../lx2160acex7/include/SD2_5.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/xspi_limit_17M.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 8 == 18 || 8 == -18
++/* protocol 18 2x-25g-6x-10g convert 2x10g-25g for 4x25g on qsfp */
++#include <../lx2160asi/sd1_lane_g_h_xfi_to_25g.rcw>
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_g.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_h.rcw>
++#endif
++
++#if 8 == 20 || 8 == -20
++/* protocol 20 dual-40g split second port into 4x10g */
++#include <../lx2160asi/e40g2_split.rcw>
++#endif
++
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0008-add-configuration-for-lx2162a-som-and-clearfog-evalu.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0008-add-configuration-for-lx2162a-som-and-clearfog-evalu.patch
new file mode 100644
index 0000000000..8800178152
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0008-add-configuration-for-lx2162a-som-and-clearfog-evalu.patch
@@ -0,0 +1,720 @@
+From 02cde01be31b429bfda95ce49d346821893418ff Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sun, 27 Oct 2024 18:26:26 +0100
+Subject: [PATCH 08/10] add configuration for lx2162a som and clearfog
+ evaluation board
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ GenerateSRConfigs.sh | 7 +
+ lx2160acex7/include/SD1_0.rcwi | 17 +++
+ lx2160acex7/include/SD2_0.rcwi | 17 +++
+ lx2160acex7/include/SD3_0.rcwi | 20 +++
+ lx2160acex7/include/pll_2000_650_xxxx.rcwi | 15 ++
+ lx2162asom_clearfog.tmpl | 25 ++++
+ lx2162asom_rev2/Makefile | 1 +
+ lx2162asom_rev2/README | 0
+ .../rcw_2000_650_2900_18_11_0_auto.rcw | 25 ++++
+ .../rcw_2000_650_2900_18_7_0_auto.rcw | 25 ++++
+ .../rcw_2000_650_2900_18_9_0_auto.rcw | 25 ++++
+ .../rcw_2000_650_2900_2_11_0_auto.rcw | 25 ++++
+ .../clearfog/rcw_2000_650_2900_2_7_0_auto.rcw | 25 ++++
+ .../clearfog/rcw_2000_650_2900_2_9_0_auto.rcw | 25 ++++
+ lx2162asom_rev2/include/SD1_18.rcwi | 18 +++
+ lx2162asom_rev2/include/SD1_2.rcwi | 22 +++
+ lx2162asom_rev2/include/SD2_11.rcwi | 29 ++++
+ lx2162asom_rev2/include/SD2_7.rcwi | 29 ++++
+ lx2162asom_rev2/include/SD2_9.rcwi | 22 +++
+ lx2162asom_rev2/include/common.rcwi | 128 ++++++++++++++++++
+ lx2162asom_rev2/include/common_pbi.rcwi | 41 ++++++
+ 21 files changed, 541 insertions(+)
+ create mode 100644 lx2160acex7/include/SD1_0.rcwi
+ create mode 100644 lx2160acex7/include/SD2_0.rcwi
+ create mode 100644 lx2160acex7/include/SD3_0.rcwi
+ create mode 100644 lx2160acex7/include/pll_2000_650_xxxx.rcwi
+ create mode 100644 lx2162asom_clearfog.tmpl
+ create mode 100644 lx2162asom_rev2/Makefile
+ create mode 100644 lx2162asom_rev2/README
+ create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw
+ create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw
+ create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw
+ create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_11_0_auto.rcw
+ create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_7_0_auto.rcw
+ create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_9_0_auto.rcw
+ create mode 100644 lx2162asom_rev2/include/SD1_18.rcwi
+ create mode 100644 lx2162asom_rev2/include/SD1_2.rcwi
+ create mode 100644 lx2162asom_rev2/include/SD2_11.rcwi
+ create mode 100644 lx2162asom_rev2/include/SD2_7.rcwi
+ create mode 100644 lx2162asom_rev2/include/SD2_9.rcwi
+ create mode 100644 lx2162asom_rev2/include/common.rcwi
+ create mode 100644 lx2162asom_rev2/include/common_pbi.rcwi
+
+diff --git a/GenerateSRConfigs.sh b/GenerateSRConfigs.sh
+index aa0ad68..342d0d7 100755
+--- a/GenerateSRConfigs.sh
++++ b/GenerateSRConfigs.sh
+@@ -60,3 +60,10 @@ for DDR_SPEED in 2400 2600 2666 2900 3200; do
+ done
+ done
+ done
++
++# generate LX2162A CSoM Clearfog
++for SD1 in 2 18; do
++ for SD2 in 7 9 11; do
++ generate lx2162asom_clearfog.tmpl lx2162asom 2 clearfog 2000 650 2900 ${SD1} ${SD2} 0 auto
++ done
++done
+diff --git a/lx2160acex7/include/SD1_0.rcwi b/lx2160acex7/include/SD1_0.rcwi
+new file mode 100644
+index 0000000..718a441
+--- /dev/null
++++ b/lx2160acex7/include/SD1_0.rcwi
+@@ -0,0 +1,17 @@
++/* Serdes 1 Protocol 0: Disabled */
++SRDS_PRTCL_S1=0
++
++/* Disable Serdes 1 PLLF */
++SRDS_PLL_PD_PLL1=1
++
++/* Disable Serdes 1 PLLF reference clock */
++SRDS_REFCLKF_DIS_S2=1
++
++/* Don't use Serdes 1 PLLF as reference for PLLS */
++SRDS_INTRA_REF_CLK_S1=0
++
++/* Disable Serdes 1 PLLS */
++SRDS_PLL_PD_PLL2=1
++
++/* Select Serdes 1 PLL Default Fequencies (don't care) */
++SRDS_PLL_REF_CLK_SEL_S1=0
+diff --git a/lx2160acex7/include/SD2_0.rcwi b/lx2160acex7/include/SD2_0.rcwi
+new file mode 100644
+index 0000000..6af65a3
+--- /dev/null
++++ b/lx2160acex7/include/SD2_0.rcwi
+@@ -0,0 +1,17 @@
++/* Serdes 2 Protocol 0: Disabled */
++SRDS_PRTCL_S2=0
++
++/* Disable Serdes 2 PLLF */
++SRDS_PLL_PD_PLL3=1
++
++/* Disable Serdes 2 PLLF reference clock */
++SRDS_REFCLKF_DIS_S2=1
++
++/* Don't use Serdes 2 PLLF as reference for PLLS */
++SRDS_INTRA_REF_CLK_S2=0
++
++/* Disable Serdes 2 PLLS */
++SRDS_PLL_PD_PLL4=1
++
++/* Select Serdes 2 PLL Default Fequencies (don't care) */
++SRDS_PLL_REF_CLK_SEL_S2=0
+diff --git a/lx2160acex7/include/SD3_0.rcwi b/lx2160acex7/include/SD3_0.rcwi
+new file mode 100644
+index 0000000..250437c
+--- /dev/null
++++ b/lx2160acex7/include/SD3_0.rcwi
+@@ -0,0 +1,20 @@
++/* Serdes 3 Protocol 0: Disabled */
++SRDS_PRTCL_S3=0
++
++/* Disable Serdes 3 PLLF */
++SRDS_PLL_PD_PLL5=1
++
++/* Disable Serdes 3 PLLF reference clock */
++SRDS_REFCLKF_DIS_S3=1
++
++/* Don't use Serdes 3 PLLF as reference for PLLS */
++SRDS_INTRA_REF_CLK_S3=0
++
++/* Disable Serdes 3 PLLS */
++SRDS_PLL_PD_PLL6=1
++
++/*
++ * Select Serdes 3 PLL Default Fequencies (don't care)
++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 936-937)
++ */
++SRDS_PLL_REF_CLK_SEL_S3=0
+diff --git a/lx2160acex7/include/pll_2000_650_xxxx.rcwi b/lx2160acex7/include/pll_2000_650_xxxx.rcwi
+new file mode 100644
+index 0000000..0bc7e8b
+--- /dev/null
++++ b/lx2160acex7/include/pll_2000_650_xxxx.rcwi
+@@ -0,0 +1,15 @@
++/*
++ * Core and Platform Clocks:
++ * - Platform: 650MHz
++ * - Core: 2000MHz
++ */
++
++/* platform clock is system clock mul 13 div 2 = 650 */
++SYS_PLL_RAT=13
++
++/* core clocks are 2000 */
++CGA_PLL1_RAT=20
++CGA_PLL2_RAT=20
++CGB_PLL1_RAT=20
++/* same as all nxp 2000_650_* */
++CGB_PLL2_RAT=8
+diff --git a/lx2162asom_clearfog.tmpl b/lx2162asom_clearfog.tmpl
+new file mode 100644
+index 0000000..073de69
+--- /dev/null
++++ b/lx2162asom_clearfog.tmpl
+@@ -0,0 +1,25 @@
++/*
++ * SerDes Protocol 1 - %SD1%
++ * SerDes Protocol 2 - %SD2%
++ *
++ * Frequencies:
++ * Core -- %CPU_SPEED% MHz
++ * Platform -- %BUS_SPEED% MHz
++ * DDR -- %DDR_SPEED% MT/s
++ *
++ * Silicon %SOC_REVISION%.0
++ * Boot from %BOOTSOURCE%
++ */
++
++#define LX_SR %SOC_REVISION%
++#define LX_BOOTSOURCE_%BOOTSOURCE%
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_%CPU_SPEED%_%BUS_SPEED%_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_%DDR_SPEED%.rcwi>
++#include <../%module%_rev%SOC_REVISION%/include/common.rcwi>
++#include <../%module%_rev%SOC_REVISION%/include/SD1_%SD1%.rcwi>
++#include <../%module%_rev%SOC_REVISION%/include/SD2_%SD2%.rcwi>
++#include <../lx2160acex7/include/SD3_0.rcwi>
++#include <../%module%_rev%SOC_REVISION%/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2162asom_rev2/Makefile b/lx2162asom_rev2/Makefile
+new file mode 100644
+index 0000000..f77e46b
+--- /dev/null
++++ b/lx2162asom_rev2/Makefile
+@@ -0,0 +1 @@
++include ../Makefile.inc
+diff --git a/lx2162asom_rev2/README b/lx2162asom_rev2/README
+new file mode 100644
+index 0000000..e69de29
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw
+new file mode 100644
+index 0000000..e79479e
+--- /dev/null
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw
+@@ -0,0 +1,25 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 11
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 650 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2162asom_rev2/include/common.rcwi>
++#include <../lx2162asom_rev2/include/SD1_18.rcwi>
++#include <../lx2162asom_rev2/include/SD2_11.rcwi>
++#include <../lx2160acex7/include/SD3_0.rcwi>
++#include <../lx2162asom_rev2/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw
+new file mode 100644
+index 0000000..4724239
+--- /dev/null
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw
+@@ -0,0 +1,25 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 7
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 650 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2162asom_rev2/include/common.rcwi>
++#include <../lx2162asom_rev2/include/SD1_18.rcwi>
++#include <../lx2162asom_rev2/include/SD2_7.rcwi>
++#include <../lx2160acex7/include/SD3_0.rcwi>
++#include <../lx2162asom_rev2/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw
+new file mode 100644
+index 0000000..3a7703d
+--- /dev/null
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw
+@@ -0,0 +1,25 @@
++/*
++ * SerDes Protocol 1 - 18
++ * SerDes Protocol 2 - 9
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 650 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2162asom_rev2/include/common.rcwi>
++#include <../lx2162asom_rev2/include/SD1_18.rcwi>
++#include <../lx2162asom_rev2/include/SD2_9.rcwi>
++#include <../lx2160acex7/include/SD3_0.rcwi>
++#include <../lx2162asom_rev2/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_11_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_11_0_auto.rcw
+new file mode 100644
+index 0000000..6a1863d
+--- /dev/null
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_11_0_auto.rcw
+@@ -0,0 +1,25 @@
++/*
++ * SerDes Protocol 1 - 2
++ * SerDes Protocol 2 - 11
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 650 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2162asom_rev2/include/common.rcwi>
++#include <../lx2162asom_rev2/include/SD1_2.rcwi>
++#include <../lx2162asom_rev2/include/SD2_11.rcwi>
++#include <../lx2160acex7/include/SD3_0.rcwi>
++#include <../lx2162asom_rev2/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_7_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_7_0_auto.rcw
+new file mode 100644
+index 0000000..24cf24a
+--- /dev/null
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_7_0_auto.rcw
+@@ -0,0 +1,25 @@
++/*
++ * SerDes Protocol 1 - 2
++ * SerDes Protocol 2 - 7
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 650 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2162asom_rev2/include/common.rcwi>
++#include <../lx2162asom_rev2/include/SD1_2.rcwi>
++#include <../lx2162asom_rev2/include/SD2_7.rcwi>
++#include <../lx2160acex7/include/SD3_0.rcwi>
++#include <../lx2162asom_rev2/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_9_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_9_0_auto.rcw
+new file mode 100644
+index 0000000..9533815
+--- /dev/null
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_9_0_auto.rcw
+@@ -0,0 +1,25 @@
++/*
++ * SerDes Protocol 1 - 2
++ * SerDes Protocol 2 - 9
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 650 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2162asom_rev2/include/common.rcwi>
++#include <../lx2162asom_rev2/include/SD1_2.rcwi>
++#include <../lx2162asom_rev2/include/SD2_9.rcwi>
++#include <../lx2160acex7/include/SD3_0.rcwi>
++#include <../lx2162asom_rev2/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2162asom_rev2/include/SD1_18.rcwi b/lx2162asom_rev2/include/SD1_18.rcwi
+new file mode 100644
+index 0000000..34c5be3
+--- /dev/null
++++ b/lx2162asom_rev2/include/SD1_18.rcwi
+@@ -0,0 +1,18 @@
++/* Serdes 1 Protocol 18: 2x10Gbps + 2x25Gbps */
++SRDS_PRTCL_S1=18
++
++/* Enable Serdes 1 PLLF */
++SRDS_PLL_PD_PLL1=0
++
++/* Enable Serdes 1 PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/* Use Serdes 1 PLLF for PLLS (LX2162A has no physical input for PLLS) */
++SRDS_INTRA_REF_CLK_S1=1
++
++/*
++ * Select Serdes 1 PLLF frequency 161.1328125MHz for 25GE mode (lanes 2+3): Bit 0 = 0
++ * Select Serdes 1 PLLS frequency 161.1328125MHz for 10GE mode (not documented in RM): Bit 1 = 1
++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=2
+diff --git a/lx2162asom_rev2/include/SD1_2.rcwi b/lx2162asom_rev2/include/SD1_2.rcwi
+new file mode 100644
+index 0000000..d2877db
+--- /dev/null
++++ b/lx2162asom_rev2/include/SD1_2.rcwi
+@@ -0,0 +1,22 @@
++/*
++ * This conmfiguration requires changing reference clock on SoM U10 from 161MHz to 100MHz.
++ */
++
++/* Serdes 1 Protocol 2: 4x1Gbps */
++SRDS_PRTCL_S1=2
++
++/* Disable Serdes 1 PLLF */
++SRDS_PLL_PD_PLL1=1
++
++/* Enable Serdes 1 PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/* Use Serdes 1 PLLF for PLLS (LX2162A has no physical input for PLLS) */
++SRDS_INTRA_REF_CLK_S1=1
++
++/*
++ * Select Serdes 1 PLLF frequency 100MHz for 1GE mode (don't care): Bit 0 = 0
++ * Select Serdes 1 PLLS frequency 100MHz for 1GE mode: Bit 1 = 0
++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=0
+diff --git a/lx2162asom_rev2/include/SD2_11.rcwi b/lx2162asom_rev2/include/SD2_11.rcwi
+new file mode 100644
+index 0000000..5d75b17
+--- /dev/null
++++ b/lx2162asom_rev2/include/SD2_11.rcwi
+@@ -0,0 +1,29 @@
++/* Serdes 2 Protocol 11: 6x1Gbps & 2x PCI-e x1 Gen 3 */
++SRDS_PRTCL_S2=11
++
++/* Enable Serdes 2 PLLF */
++SRDS_PLL_PD_PLL3=0
++
++/* Enable Serdes 2 PLLS */
++SRDS_PLL_PD_PLL4=0
++
++/* Use Serdes 2 PLLF for PLLS (to share PLLF 100MHz reference clock) */
++SRDS_INTRA_REF_CLK_S2=1
++
++/*
++ * Select Serdes 2 PLLF frequency 100MHz for PCI: Bit 0 = 0
++ * Select Serdes 2 PLLS frequency 100MHz for 1G mode: Bit 1 = 0
++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935)
++ */
++SRDS_PLL_REF_CLK_SEL_S2=0
++
++/* Support up to PCI-e Gen 3 */
++SRDS_DIV_PEX_S2=1
++
++/* Configure Ethernet Controllers 1+2 Pins as GPIOs to avoid competing for WRIO MACs 17+18 */
++EC1_PMUX=1
++EC2_PMUX=1
++
++/* indicate PCI ports for pbi section errata application*/
++#define HAVE_PEX3
++#define HAVE_PEX4
+diff --git a/lx2162asom_rev2/include/SD2_7.rcwi b/lx2162asom_rev2/include/SD2_7.rcwi
+new file mode 100644
+index 0000000..763a64a
+--- /dev/null
++++ b/lx2162asom_rev2/include/SD2_7.rcwi
+@@ -0,0 +1,29 @@
++/* Serdes 2 Protocol 7: 2x10Gbps 4x1Gbps & 2x PCI-e x1 Gen 2 */
++SRDS_PRTCL_S2=7
++
++/* Enable Serdes 2 PLLF */
++SRDS_PLL_PD_PLL3=0
++
++/* Enable Serdes 2 PLLS */
++SRDS_PLL_PD_PLL4=0
++
++/* Don't use Serdes 2 PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S2=0
++
++/*
++ * Select Serdes 2 PLLF frequency 100MHz for 1G (and pcie): Bit 0 = 0
++ * Select Serdes 2 PLLS frequency 156.25MHz for 10G mode: Bit 1 = 0
++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935)
++ */
++SRDS_PLL_REF_CLK_SEL_S2=0
++
++/* Support up to PCI-e Gen 2 */
++SRDS_DIV_PEX_S2=2
++
++/* Configure Ethernet Controllers 1+2 Pins as GPIOs to avoid competing for WRIO MACs 17+18 */
++EC1_PMUX=1
++EC2_PMUX=1
++
++/* indicate PCI ports for pbi section errata application*/
++#define HAVE_PEX3
++#define HAVE_PEX4
+diff --git a/lx2162asom_rev2/include/SD2_9.rcwi b/lx2162asom_rev2/include/SD2_9.rcwi
+new file mode 100644
+index 0000000..68728ba
+--- /dev/null
++++ b/lx2162asom_rev2/include/SD2_9.rcwi
+@@ -0,0 +1,22 @@
++/* Serdes 2 Protocol 9: 8x1Gbps */
++SRDS_PRTCL_S2=9
++
++/* Disable Serdes 2 PLLF */
++SRDS_PLL_PD_PLL3=1
++
++/* Enable Serdes 2 PLLS */
++SRDS_PLL_PD_PLL4=0
++
++/* Use Serdes 2 PLLF for PLLS (to share PLLF 100MHz reference clock) */
++SRDS_INTRA_REF_CLK_S2=1
++
++/*
++ * Select Serdes 2 PLLF frequency 100MHz (don't care): Bit 0 = 0
++ * Select Serdes 2 PLLS frequency 100MHz for 1G mode: Bit 1 = 0
++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935)
++ */
++SRDS_PLL_REF_CLK_SEL_S2=0
++
++/* Configure Ethernet Controllers 1+2 Pins as GPIOs to avoid competing for WRIO MACs 17+18 */
++EC1_PMUX=1
++EC2_PMUX=1
+diff --git a/lx2162asom_rev2/include/common.rcwi b/lx2162asom_rev2/include/common.rcwi
+new file mode 100644
+index 0000000..35a6db6
+--- /dev/null
++++ b/lx2162asom_rev2/include/common.rcwi
+@@ -0,0 +1,128 @@
++/*
++ * LX2162A SoM Common Configuration
++ */
++
++/* C[5:8]_PLL are CG[5:8] div 1 */
++C5_PLL_SEL=0
++C6_PLL_SEL=0
++C7_PLL_SEL=0
++C8_PLL_SEL=0
++/* Cluster group A clock is PLL1 div 1 (unused on LX2160A) */
++HWA_CGA_M1_CLK_SEL=1
++/* Cluster group B clock is PLL2 div 2 (for DCE) */
++HWA_CGB_M1_CLK_SEL=6
++/*
++ * fall-back boot-mode when DCFG boot location pointer registers are null
++ * - 0b10101 (21): OCRAM
++ * - 0b11010 (26): XSPI
++ */
++BOOT_LOC=21
++/* SYSCLK is 100MHz */
++SYSCLK_FREQ=600
++/* USB-3.0 clock is 100MHz */
++USB3_CLK_FSEL=39
++
++/* IIC1 is I2C */
++IIC1_PMUX=0
++/* IIC2 is SD Card-Detect */
++IIC2_PMUX=6
++/* IIC3 is I2C */
++IIC3_PMUX=0
++/* IIC4 is I2C (unused) */
++IIC4_PMUX=0
++/* IIC5 is I2C */
++IIC5_PMUX=0
++/* IIC6 is I2C (unused) */
++IIC6_PMUX=0
++/*
++ * SDHC1 CMD/CLK/VBUS/DAT[0:3] are SDHC
++ * SPI3_PCS0 is VSEL
++ */
++SDHC1_BASE_PMUX=0
++/* SDHC1_DS is GPIO (unused) */
++SDHC1_DS_PMUX=1
++/* SDHC1_CMD/DAT0/DAT1_DIR (SPI3_PCS[1:3]) are GPIO1[14:12] */
++SDHC1_DIR_PMUX=1
++/* USB[1:2]_DRVVBUS/PWRFAULT are GPIO4[28:25] (unused) */
++USB_EXT_PMUX=1
++/* XSPI1_A_DQS/SCK/CS0_B/CS1_B are SPI */
++XSPI1_A_BASE_PMUX=0
++/* XSPI1_A_DATA[3:0] are SPI */
++XSPI1_A_DATA30_PMUX=0
++/* XSPI1_A_DATA[7:4] are SPI */
++XSPI1_A_DATA74_PMUX=0
++/* ASLEEP is ASLEEP (unused) */
++ASLEEP_PMUX=0
++/* EVT[2:0] are GPIO3[14:12] */
++EVT20_PMUX=1
++/* EVT[4:3] are GPIO3[16:15] */
++EVT43_PMUX=1
++/* CLK_OUT is GPIO (unused) */
++CLK_OUT_PMUX=1
++/* IRQ[3:0] are GPIO3[3:0] */
++IRQ03_00_PMUX=1
++/* IRQ[7:4] are GPIO3[7:4] */
++IRQ07_04_PMUX=1
++/* IRQ[11:8] are GPIO3[11:8] */
++IRQ11_08_PMUX=1
++/* EC1_* are RGMII */
++EC1_PMUX=0
++/* EC2_* are PTP */
++EC2_PMUX=2
++/* EC_GTX_CLK125 is PTP */
++GTX_CLK_PMUX=0
++/* UART1_SOUT/SIN are UART1 */
++UART1_SOUTSIN_PMUX=0
++/* UART1_RTS/CTS_B are GPIO (unused) */
++UART1_RTSCTS_PMUX=1
++/* UART2_SOUT/SIN are UART2 */
++UART2_SOUTSIN_PMUX=0
++/* UART2_RTS/CTS_B are GPIO (unused) */
++UART2_RTSCTS_PMUX=1
++/* SDHC2_CMD/DAT[3:0]/DS/CLK are SDHC */
++SDHC2_BASE_PMUX=0
++/* SDHC2_DAT[7:4] are SDHC */
++SDHC2_DAT74_PMUX=0
++
++
++/* configure IIC1, IIC3, IIC5, IIC6 pins for i2c */
++IIC1_PMUX=0
++IIC3_PMUX=0
++IIC5_PMUX=0
++IIC6_PMUX=0
++
++/*
++ * Configure GPIOs:
++ * EVT0_B: GPIO3_DAT12
++ * EVT1_B: GPIO3_DAT13 (SFP 25 upper LED)
++ * EVT2_B: GPIO3_DAT14 (SFP 25 lower LED)
++ * EVT3_B: GPIO3_DAT15 (SFP 25 lower MODABS)
++ * EVT4_B: GPIO3_DAT16 (SFP 10 upper MODABS)
++ * PROC_IRQ0: GPIO3_DAT00
++ * PROC_IRQ1: GPIO3_DAT01 (SFP 10 lower MODABS)
++ * PROC_IRQ2: GPIO3_DAT02
++ * PROC_IRQ3: GPIO3_DAT03
++ * PROC_IRQ4: GPIO3_DAT04
++ * PROC_IRQ5: GPIO3_DAT05 (SFP 10 upper LED)
++ * PROC_IRQ6: GPIO3_DAT06
++ * PROC_IRQ7: GPIO3_DAT07
++ * PROC_IRQ8: GPIO3_DAT08
++ * PROC_IRQ9: GPIO3_DAT09
++ * PROC_IRQ10: GPIO3_DAT10 (SFP 25 upper MODABS)
++ * PROC_IRQ11: GPIO3_DAT11 (SFP 10 lower LED)
++ */
++EVT20_PMUX=1
++EVT43_PMUX=1
++IRQ03_00_PMUX=1
++IRQ07_04_PMUX=1
++IRQ11_08_PMUX=1
++
++/* Configure USB1 Pins for USB */
++USB_EXT_PMUX=0
++
++
++/*
++ * Original SolidRun Settings in LSDK-21.08
++ *
++ * HWA_CGB_M1_CLK_SEL=7 // Cluster Group B PLL 2 / 3 is clock
++ */
+diff --git a/lx2162asom_rev2/include/common_pbi.rcwi b/lx2162asom_rev2/include/common_pbi.rcwi
+new file mode 100644
+index 0000000..b313c1e
+--- /dev/null
++++ b/lx2162asom_rev2/include/common_pbi.rcwi
+@@ -0,0 +1,41 @@
++/*
++ * LX2162A SoM Common Configuration
++ */
++
++/* Errata to write on scratch reg for validation */
++#include <../lx2160asi/scratchrw1.rcw>
++
++/* common PBI commands */
++#include <../lx2160asi/common.rcw>
++
++/* PCIe Errata A-009531, A-008851 */
++#ifdef HAVE_PEX1
++#include <../lx2160asi/a009531_PEX1.rcw>
++#include <../lx2160asi/a008851_PEX1.rcw>
++#endif
++#ifdef HAVE_PEX3
++#include <../lx2160asi/a009531_PEX3.rcw>
++#include <../lx2160asi/a008851_PEX3.rcw>
++#endif
++#ifdef HAVE_PEX4
++#include <../lx2160asi/a009531_PEX4.rcw>
++#include <../lx2160asi/a008851_PEX4.rcw>
++#endif
++
++/* SerDes Errata A-050479 */
++#include <../lx2160asi/a050479.rcw>
++
++/* PEX2/5/6 clock disable (not available on LX2162) */
++#include <../lx2162aqds/disable_pci2_5_6.rcw>
++
++/* USB2 clock disable (not available on LX2162) */
++#include <../lx2162aqds/disable_usb2.rcw>
++
++/* MAC7 to MAC10 clock disable (not available on LX2162) */
++#include <../lx2162aqds/disable_mac7_10.rcw>
++
++/* DDR2 clock disable*/
++#include <../lx2162aqds/disable_ddr2.rcw>
++
++/* Errata A-050426 */
++#include <../lx2160asi/a050426.rcw>
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0009-add-configuration-solidrun-internal-lx2160a-cex6-eva.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0009-add-configuration-solidrun-internal-lx2160a-cex6-eva.patch
new file mode 100644
index 0000000000..d752e1eff8
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0009-add-configuration-solidrun-internal-lx2160a-cex6-eva.patch
@@ -0,0 +1,518 @@
+From d960a444988effbe015ab71fed3d932384a45e1b Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Fri, 11 Oct 2024 16:39:12 +0200
+Subject: [PATCH 09/10] add configuration solidrun internal lx2160a-cex6
+ evaluation board
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ GenerateSRConfigs.sh | 6 ++
+ lx2160acex6_evb.tmpl | 26 ++++++
+ lx2160acex6_rev2/Makefile | 1 +
+ lx2160acex6_rev2/README | 0
+ .../evb/rcw_2000_700_2400_3_3_2_auto.rcw | 26 ++++++
+ .../evb/rcw_2000_700_2600_3_3_2_auto.rcw | 26 ++++++
+ .../evb/rcw_2000_700_2900_3_3_2_auto.rcw | 26 ++++++
+ .../evb/rcw_2000_700_3200_3_3_2_auto.rcw | 26 ++++++
+ .../evb/rcw_2200_750_2400_3_3_2_auto.rcw | 26 ++++++
+ .../evb/rcw_2200_750_2600_3_3_2_auto.rcw | 26 ++++++
+ .../evb/rcw_2200_750_2900_3_3_2_auto.rcw | 26 ++++++
+ .../evb/rcw_2200_750_3200_3_3_2_auto.rcw | 26 ++++++
+ lx2160acex6_rev2/include/common.rcwi | 88 +++++++++++++++++++
+ lx2160acex7/include/SD1_3.rcwi | 30 +++++++
+ lx2160acex7/include/SD2_3.rcwi | 28 ++++++
+ 15 files changed, 387 insertions(+)
+ create mode 100644 lx2160acex6_evb.tmpl
+ create mode 100644 lx2160acex6_rev2/Makefile
+ create mode 100644 lx2160acex6_rev2/README
+ create mode 100644 lx2160acex6_rev2/evb/rcw_2000_700_2400_3_3_2_auto.rcw
+ create mode 100644 lx2160acex6_rev2/evb/rcw_2000_700_2600_3_3_2_auto.rcw
+ create mode 100644 lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw
+ create mode 100644 lx2160acex6_rev2/evb/rcw_2000_700_3200_3_3_2_auto.rcw
+ create mode 100644 lx2160acex6_rev2/evb/rcw_2200_750_2400_3_3_2_auto.rcw
+ create mode 100644 lx2160acex6_rev2/evb/rcw_2200_750_2600_3_3_2_auto.rcw
+ create mode 100644 lx2160acex6_rev2/evb/rcw_2200_750_2900_3_3_2_auto.rcw
+ create mode 100644 lx2160acex6_rev2/evb/rcw_2200_750_3200_3_3_2_auto.rcw
+ create mode 100644 lx2160acex6_rev2/include/common.rcwi
+ create mode 100644 lx2160acex7/include/SD1_3.rcwi
+ create mode 100644 lx2160acex7/include/SD2_3.rcwi
+
+diff --git a/GenerateSRConfigs.sh b/GenerateSRConfigs.sh
+index 342d0d7..d1afa7b 100755
+--- a/GenerateSRConfigs.sh
++++ b/GenerateSRConfigs.sh
+@@ -67,3 +67,9 @@ for SD1 in 2 18; do
+ generate lx2162asom_clearfog.tmpl lx2162asom 2 clearfog 2000 650 2900 ${SD1} ${SD2} 0 auto
+ done
+ done
++
++# generate LX2160A CEX-6 Internal Evaluation Board
++for DDR_SPEED in 2400 2600 2900 3200; do
++ generate lx2160acex6_evb.tmpl lx2160acex6 2 evb 2000 700 ${DDR_SPEED} 3 3 2 auto
++ generate lx2160acex6_evb.tmpl lx2160acex6 2 evb 2200 750 ${DDR_SPEED} 3 3 2 auto
++done
+diff --git a/lx2160acex6_evb.tmpl b/lx2160acex6_evb.tmpl
+new file mode 100644
+index 0000000..ec1c309
+--- /dev/null
++++ b/lx2160acex6_evb.tmpl
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - %SD1%
++ * SerDes Protocol 2 - %SD2%
++ * SerDes Protocol 3 - %SD3%
++ *
++ * Frequencies:
++ * Core -- %CPU_SPEED% MHz
++ * Platform -- %BUS_SPEED% MHz
++ * DDR -- %DDR_SPEED% MT/s
++ *
++ * Silicon %SOC_REVISION%.0
++ * Boot from %BOOTSOURCE%
++ */
++
++#define LX_SR %SOC_REVISION%
++#define LX_BOOTSOURCE_%BOOTSOURCE%
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_%CPU_SPEED%_%BUS_SPEED%_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_%DDR_SPEED%.rcwi>
++#include <../%module%_rev%SOC_REVISION%/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_%SD1%.rcwi>
++#include <../lx2160acex7/include/SD2_%SD2%.rcwi>
++#include <../lx2160acex7/include/SD3_%SD3%.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex6_rev2/Makefile b/lx2160acex6_rev2/Makefile
+new file mode 100644
+index 0000000..f77e46b
+--- /dev/null
++++ b/lx2160acex6_rev2/Makefile
+@@ -0,0 +1 @@
++include ../Makefile.inc
+diff --git a/lx2160acex6_rev2/README b/lx2160acex6_rev2/README
+new file mode 100644
+index 0000000..e69de29
+diff --git a/lx2160acex6_rev2/evb/rcw_2000_700_2400_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2000_700_2400_3_3_2_auto.rcw
+new file mode 100644
+index 0000000..669cdfe
+--- /dev/null
++++ b/lx2160acex6_rev2/evb/rcw_2000_700_2400_3_3_2_auto.rcw
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - 3
++ * SerDes Protocol 2 - 3
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex6_rev2/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_3.rcwi>
++#include <../lx2160acex7/include/SD2_3.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex6_rev2/evb/rcw_2000_700_2600_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2000_700_2600_3_3_2_auto.rcw
+new file mode 100644
+index 0000000..e95928a
+--- /dev/null
++++ b/lx2160acex6_rev2/evb/rcw_2000_700_2600_3_3_2_auto.rcw
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - 3
++ * SerDes Protocol 2 - 3
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex6_rev2/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_3.rcwi>
++#include <../lx2160acex7/include/SD2_3.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw
+new file mode 100644
+index 0000000..17e2a5c
+--- /dev/null
++++ b/lx2160acex6_rev2/evb/rcw_2000_700_2900_3_3_2_auto.rcw
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - 3
++ * SerDes Protocol 2 - 3
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex6_rev2/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_3.rcwi>
++#include <../lx2160acex7/include/SD2_3.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex6_rev2/evb/rcw_2000_700_3200_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2000_700_3200_3_3_2_auto.rcw
+new file mode 100644
+index 0000000..c51bb5e
+--- /dev/null
++++ b/lx2160acex6_rev2/evb/rcw_2000_700_3200_3_3_2_auto.rcw
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - 3
++ * SerDes Protocol 2 - 3
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex6_rev2/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_3.rcwi>
++#include <../lx2160acex7/include/SD2_3.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex6_rev2/evb/rcw_2200_750_2400_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2200_750_2400_3_3_2_auto.rcw
+new file mode 100644
+index 0000000..2950cba
+--- /dev/null
++++ b/lx2160acex6_rev2/evb/rcw_2200_750_2400_3_3_2_auto.rcw
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - 3
++ * SerDes Protocol 2 - 3
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex6_rev2/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_3.rcwi>
++#include <../lx2160acex7/include/SD2_3.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex6_rev2/evb/rcw_2200_750_2600_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2200_750_2600_3_3_2_auto.rcw
+new file mode 100644
+index 0000000..a814a9f
+--- /dev/null
++++ b/lx2160acex6_rev2/evb/rcw_2200_750_2600_3_3_2_auto.rcw
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - 3
++ * SerDes Protocol 2 - 3
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex6_rev2/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_3.rcwi>
++#include <../lx2160acex7/include/SD2_3.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex6_rev2/evb/rcw_2200_750_2900_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2200_750_2900_3_3_2_auto.rcw
+new file mode 100644
+index 0000000..af4ab0a
+--- /dev/null
++++ b/lx2160acex6_rev2/evb/rcw_2200_750_2900_3_3_2_auto.rcw
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - 3
++ * SerDes Protocol 2 - 3
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex6_rev2/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_3.rcwi>
++#include <../lx2160acex7/include/SD2_3.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex6_rev2/evb/rcw_2200_750_3200_3_3_2_auto.rcw b/lx2160acex6_rev2/evb/rcw_2200_750_3200_3_3_2_auto.rcw
+new file mode 100644
+index 0000000..5e088e6
+--- /dev/null
++++ b/lx2160acex6_rev2/evb/rcw_2200_750_3200_3_3_2_auto.rcw
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - 3
++ * SerDes Protocol 2 - 3
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2200 MHz
++ * Platform -- 750 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex6_rev2/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_3.rcwi>
++#include <../lx2160acex7/include/SD2_3.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex6_rev2/include/common.rcwi b/lx2160acex6_rev2/include/common.rcwi
+new file mode 100644
+index 0000000..8cc5ec7
+--- /dev/null
++++ b/lx2160acex6_rev2/include/common.rcwi
+@@ -0,0 +1,88 @@
++/*
++ * LX2160A COM-Express Type 6 Common Configuration
++ */
++
++/* C[5:8]_PLL are CG[5:8] div 1 */
++C5_PLL_SEL=0
++C6_PLL_SEL=0
++C7_PLL_SEL=0
++C8_PLL_SEL=0
++/* Cluster group A clock is PLL1 div 1 (unused on LX2160A) */
++HWA_CGA_M1_CLK_SEL=1
++/* Cluster group B clock is PLL2 div 2 (for DCE) */
++HWA_CGB_M1_CLK_SEL=6
++/*
++ * fall-back boot-mode when DCFG boot location pointer registers are null
++ * - 0b10101 (21): OCRAM
++ * - 0b11010 (26): XSPI
++ */
++BOOT_LOC=21
++/* SYSCLK is 100MHz */
++SYSCLK_FREQ=600
++/* USB-3.0 clock is 100MHz */
++USB3_CLK_FSEL=39
++
++/* IIC1 is I2C */
++IIC1_PMUX=0
++/* IIC2 is SD Card-Detect */
++IIC2_PMUX=6
++/* IIC3 is I2C */
++IIC3_PMUX=0
++/* IIC4 is I2C */
++IIC4_PMUX=0
++/* IIC5 SCL/SDA are SPI3_SOUT/SPI3_SIN */
++IIC5_PMUX=3
++/* IIC6 is PHY reset gpio */
++IIC6_PMUX=1
++/* SDHC1 CMD/CLK/DAT[0:3]/VSEL are SDHC1 CMD/CLK/DAT[0:3]/SPI3_PCS0 */
++SDHC1_BASE_PMUX=3
++/* SDHC1_DS is SPI3_SCK */
++SDHC1_DS_PMUX=2
++/* SDHC1_CMD_DIR (A4) / SDHC1_DAT0_DIR (B3) / SDHC1_DAT123_DIR (C3) are SPI3_PCS[1:3] */
++SDHC1_DIR_PMUX=3
++/* USB[1:2]_DRVVBUS/PWRFAULT are GPIO4[28:25] (unused) */
++USB_EXT_PMUX=1
++/* XSPI1_A_DQS/SCK/CS0_B/CS1_B are SPI */
++XSPI1_A_BASE_PMUX=0
++/* XSPI1_A_DATA[3:0] are SPI */
++XSPI1_A_DATA30_PMUX=0
++/* XSPI1_A_DATA[7:4] are SPI */
++XSPI1_A_DATA74_PMUX=0
++/* ASLEEP is ASLEEP (unused, bootstrap) */
++ASLEEP_PMUX=0
++/* EVT[2:0] are GPIO3[14:12] */
++EVT20_PMUX=1
++/* EVT[4:3] are GPIO3[16:15] */
++EVT43_PMUX=1
++/* CLK_OUT is GPIO (unused) */
++CLK_OUT_PMUX=1
++/* IRQ[3:0] are GPIO3[3:0] */
++IRQ03_00_PMUX=1
++/* IRQ[7:4] are GPIO3[7:4] */
++IRQ07_04_PMUX=1
++/* IRQ[11:8] are GPIO3[11:8] */
++IRQ11_08_PMUX=1
++/* EC1_* are RGMII */
++EC1_PMUX=0
++/* EC2_* are GPIO4[23:12] */
++EC2_PMUX=1
++/* EC_GTX_CLK125 is PTP */
++GTX_CLK_PMUX=0
++/* UART1_SOUT/SIN are UART1 */
++UART1_SOUTSIN_PMUX=0
++/* UART1_RTS/CTS_B are UART3_SOUT/SIN */
++UART1_RTSCTS_PMUX=2
++/* UART2_SOUT/SIN are UART2 */
++UART2_SOUTSIN_PMUX=0
++/* UART2_RTS/CTS_B are UART4_SOUT/SIN */
++UART2_RTSCTS_PMUX=2
++/* SDHC2_CMD/DAT[3:0]/DS/CLK are SDHC */
++SDHC2_BASE_PMUX=0
++/* SDHC2_DAT[7:4] are SDHC */
++SDHC2_DAT74_PMUX=0
++
++/*
++ * Original SolidRun Settings in LSDK-21.08
++ *
++ * HWA_CGB_M1_CLK_SEL=7 // Cluster Group B PLL 2 / 3 is clock
++ */
+diff --git a/lx2160acex7/include/SD1_3.rcwi b/lx2160acex7/include/SD1_3.rcwi
+new file mode 100644
+index 0000000..73efe29
+--- /dev/null
++++ b/lx2160acex7/include/SD1_3.rcwi
+@@ -0,0 +1,30 @@
++/*
++ * Serdes 1 Reference Clocks:
++ * - PLLF = 100MHz
++ * - PLLS = 161.1328125MHz
++ */
++
++/* Serdes 1 Protocol 3: 4x10Gbps + 1xPCI-e-x4 */
++SRDS_PRTCL_S1=3
++
++/* Enable Serdes 1 PLLF */
++SRDS_PLL_PD_PLL1=0
++
++/* Don't use Serdes 1 PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S1=0
++
++/* Enable Serdes 1 PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/*
++ * Select Serdes 1 PLLF frequency 100MHz for pcie: Bit 0 = 0
++ * Select Serdes 1 PLLS frequency 161.1328125MHz (not documented in RM) for usxgmii: Bit 1 = 1
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=2
++
++/* Support up to PCI-e Gen 3 */
++SRDS_DIV_PEX_S1=1
++
++/* indicate PCI ports for pbi section errata application*/
++#define HAVE_PEX2
+diff --git a/lx2160acex7/include/SD2_3.rcwi b/lx2160acex7/include/SD2_3.rcwi
+new file mode 100644
+index 0000000..ec018b4
+--- /dev/null
++++ b/lx2160acex7/include/SD2_3.rcwi
+@@ -0,0 +1,28 @@
++/*
++ * Serdes 2 Reference Clocks:
++ * - PLLF = 100MHz
++ * - PLLS = 100MHz
++ */
++
++/* Serdes 2 Protocol 3: 2xPCI-e-x4 */
++SRDS_PRTCL_S2=3
++
++/* Enable Serdes 2 PLLF */
++SRDS_PLL_PD_PLL3=0
++
++/* Enable Serdes 2 PLLS */
++SRDS_PLL_PD_PLL4=0
++
++/* Don't use Serdes 2 PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S2=0
++
++/*
++ * Select Serdes 2 PLLF frequency 100MHz (Bit 0)
++ * Select Serdes 2 PLLS frequency 100MHz (Bit 1)
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S2=0
++
++/* indicate PCI ports for pbi section errata application*/
++#define HAVE_PEX3
++#define HAVE_PEX4
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0010-add-configuration-solidrun-internal-lx2160acex7-twin.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0010-add-configuration-solidrun-internal-lx2160acex7-twin.patch
new file mode 100644
index 0000000000..3c5b66f405
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0010-add-configuration-solidrun-internal-lx2160acex7-twin.patch
@@ -0,0 +1,269 @@
+From bc8e352efbc32a584f023f5818d9d6ee1503be1e Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sat, 9 Aug 2025 16:53:43 +0200
+Subject: [PATCH 10/10] add configuration solidrun internal lx2160acex7 twins
+ board
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ GenerateSRConfigs.sh | 5 ++++
+ lx2160acex7/include/SD2_9.rcwi | 30 +++++++++++++++++++
+ .../twins/rcw_2000_700_2400_8S_9_2_auto.rcw | 26 ++++++++++++++++
+ .../twins/rcw_2000_700_2600_8S_9_2_auto.rcw | 26 ++++++++++++++++
+ .../twins/rcw_2000_700_2666_8S_9_2_auto.rcw | 26 ++++++++++++++++
+ .../twins/rcw_2000_700_2900_8S_9_2_auto.rcw | 26 ++++++++++++++++
+ .../twins/rcw_2000_700_3200_8S_9_2_auto.rcw | 26 ++++++++++++++++
+ lx2160acex7_twins.tmpl | 26 ++++++++++++++++
+ 8 files changed, 191 insertions(+)
+ create mode 100644 lx2160acex7/include/SD2_9.rcwi
+ create mode 100644 lx2160acex7_rev2/twins/rcw_2000_700_2400_8S_9_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/twins/rcw_2000_700_2600_8S_9_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/twins/rcw_2000_700_2666_8S_9_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/twins/rcw_2000_700_2900_8S_9_2_auto.rcw
+ create mode 100644 lx2160acex7_rev2/twins/rcw_2000_700_3200_8S_9_2_auto.rcw
+ create mode 100644 lx2160acex7_twins.tmpl
+
+diff --git a/GenerateSRConfigs.sh b/GenerateSRConfigs.sh
+index d1afa7b..8d1aaea 100755
+--- a/GenerateSRConfigs.sh
++++ b/GenerateSRConfigs.sh
+@@ -73,3 +73,8 @@ for DDR_SPEED in 2400 2600 2900 3200; do
+ generate lx2160acex6_evb.tmpl lx2160acex6 2 evb 2000 700 ${DDR_SPEED} 3 3 2 auto
+ generate lx2160acex6_evb.tmpl lx2160acex6 2 evb 2200 750 ${DDR_SPEED} 3 3 2 auto
+ done
++
++# generate LX2160A CEX-7 Internal Twins Board
++for DDR_SPEED in 2400 2600 2666 2900 3200; do
++ generate lx2160acex7_twins.tmpl lx2160acex7 2 twins 2000 700 ${DDR_SPEED} 8S 9 2 auto
++done
+diff --git a/lx2160acex7/include/SD2_9.rcwi b/lx2160acex7/include/SD2_9.rcwi
+new file mode 100644
+index 0000000..b3722a0
+--- /dev/null
++++ b/lx2160acex7/include/SD2_9.rcwi
+@@ -0,0 +1,30 @@
++/*
++ * Serdes 2 Reference Clocks:
++ * - PLLF = 100MHz
++ * - PLLS = 100MHz
++ */
++
++/* Serdes 2 Protocol 9: 8x1Gbps */
++SRDS_PRTCL_S2=9
++
++/* Enable PLLF */
++SRDS_PLL_PD_PLL3=0
++
++/* Don't use PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S2=0
++
++/* Enable PLLS */
++SRDS_PLL_PD_PLL4=0
++
++/*
++ * Select PLLF frequency 100MHz: Bit 0 = 0
++ * Select PLLS frequency 100MHz: Bit 1 = 0
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 934-935)
++ */
++SRDS_PLL_REF_CLK_SEL_S2=0
++
++/* Support up to PCI-e Gen 3 */
++SRDS_DIV_PEX_S2=1
++
++/* Configure Ethernet Controller 1 Pins as GPIOs to avoid competing for WRIO MAC 17 */
++EC1_PMUX=1
+diff --git a/lx2160acex7_rev2/twins/rcw_2000_700_2400_8S_9_2_auto.rcw b/lx2160acex7_rev2/twins/rcw_2000_700_2400_8S_9_2_auto.rcw
+new file mode 100644
+index 0000000..3e39c19
+--- /dev/null
++++ b/lx2160acex7_rev2/twins/rcw_2000_700_2400_8S_9_2_auto.rcw
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 9
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2400 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_9.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex7_rev2/twins/rcw_2000_700_2600_8S_9_2_auto.rcw b/lx2160acex7_rev2/twins/rcw_2000_700_2600_8S_9_2_auto.rcw
+new file mode 100644
+index 0000000..dd38456
+--- /dev/null
++++ b/lx2160acex7_rev2/twins/rcw_2000_700_2600_8S_9_2_auto.rcw
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 9
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2600 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_9.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex7_rev2/twins/rcw_2000_700_2666_8S_9_2_auto.rcw b/lx2160acex7_rev2/twins/rcw_2000_700_2666_8S_9_2_auto.rcw
+new file mode 100644
+index 0000000..2a73cd4
+--- /dev/null
++++ b/lx2160acex7_rev2/twins/rcw_2000_700_2666_8S_9_2_auto.rcw
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 9
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2666 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_9.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex7_rev2/twins/rcw_2000_700_2900_8S_9_2_auto.rcw b/lx2160acex7_rev2/twins/rcw_2000_700_2900_8S_9_2_auto.rcw
+new file mode 100644
+index 0000000..4dd4c9b
+--- /dev/null
++++ b/lx2160acex7_rev2/twins/rcw_2000_700_2900_8S_9_2_auto.rcw
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 9
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 2900 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_9.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex7_rev2/twins/rcw_2000_700_3200_8S_9_2_auto.rcw b/lx2160acex7_rev2/twins/rcw_2000_700_3200_8S_9_2_auto.rcw
+new file mode 100644
+index 0000000..3eb73e4
+--- /dev/null
++++ b/lx2160acex7_rev2/twins/rcw_2000_700_3200_8S_9_2_auto.rcw
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - 8S
++ * SerDes Protocol 2 - 9
++ * SerDes Protocol 3 - 2
++ *
++ * Frequencies:
++ * Core -- 2000 MHz
++ * Platform -- 700 MHz
++ * DDR -- 3200 MT/s
++ *
++ * Silicon 2.0
++ * Boot from AUTO
++ */
++
++#define LX_SR 2
++#define LX_BOOTSOURCE_AUTO
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi>
++#include <../lx2160acex7/include/common.rcwi>
++#include <../lx2160acex7/include/SD1_8S.rcwi>
++#include <../lx2160acex7/include/SD2_9.rcwi>
++#include <../lx2160acex7/include/SD3_2.rcwi>
++#include <../lx2160acex7/include/common_pbi.rcwi>
++#include <../lx2160acex7/include/bootlocptr.rcwi>
+diff --git a/lx2160acex7_twins.tmpl b/lx2160acex7_twins.tmpl
+new file mode 100644
+index 0000000..f2fa9ab
+--- /dev/null
++++ b/lx2160acex7_twins.tmpl
+@@ -0,0 +1,26 @@
++/*
++ * SerDes Protocol 1 - %SD1%
++ * SerDes Protocol 2 - %SD2%
++ * SerDes Protocol 3 - %SD3%
++ *
++ * Frequencies:
++ * Core -- %CPU_SPEED% MHz
++ * Platform -- %BUS_SPEED% MHz
++ * DDR -- %DDR_SPEED% MT/s
++ *
++ * Silicon %SOC_REVISION%.0
++ * Boot from %BOOTSOURCE%
++ */
++
++#define LX_SR %SOC_REVISION%
++#define LX_BOOTSOURCE_%BOOTSOURCE%
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../%module%/include/pll_%CPU_SPEED%_%BUS_SPEED%_xxxx.rcwi>
++#include <../%module%/include/pll_xxxx_xxx_%DDR_SPEED%.rcwi>
++#include <../%module%/include/common.rcwi>
++#include <../%module%/include/SD1_%SD1%.rcwi>
++#include <../%module%/include/SD2_%SD2%.rcwi>
++#include <../%module%/include/SD3_%SD3%.rcwi>
++#include <../%module%/include/common_pbi.rcwi>
++#include <../%module%/include/bootlocptr.rcwi>
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/qoriq-rcw/0011-lx2162asom_rev2-disable-mac7-10-apply-mac5-6-default.patch b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0011-lx2162asom_rev2-disable-mac7-10-apply-mac5-6-default.patch
new file mode 100644
index 0000000000..7c3a7d9417
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/qoriq-rcw/0011-lx2162asom_rev2-disable-mac7-10-apply-mac5-6-default.patch
@@ -0,0 +1,133 @@
+From e9987f2acfe75e1424afada18c9ace377755acf4 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Wed, 27 Aug 2025 17:12:54 +0200
+Subject: [PATCH] lx2162asom_rev2: disable mac7-10, apply mac5-6 default eq
+ params for 25g
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ lx2162asom_clearfog.tmpl | 6 ++++++
+ lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw | 6 ++++++
+ lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw | 6 ++++++
+ lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw | 6 ++++++
+ lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_11_0_auto.rcw | 6 ++++++
+ lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_7_0_auto.rcw | 6 ++++++
+ lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_9_0_auto.rcw | 6 ++++++
+ lx2162asom_rev2/include/common_pbi.rcwi | 3 +++
+ 8 files changed, 45 insertions(+)
+
+diff --git a/lx2162asom_clearfog.tmpl b/lx2162asom_clearfog.tmpl
+index 073de69..ce05689 100644
+--- a/lx2162asom_clearfog.tmpl
++++ b/lx2162asom_clearfog.tmpl
+@@ -23,3 +23,9 @@
+ #include <../lx2160acex7/include/SD3_0.rcwi>
+ #include <../%module%_rev%SOC_REVISION%/include/common_pbi.rcwi>
+ #include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if %nSD1% == 18 || %nSD1% == -18
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#endif
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw
+index e79479e..e61c6e5 100644
+--- a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_11_0_auto.rcw
+@@ -23,3 +23,9 @@
+ #include <../lx2160acex7/include/SD3_0.rcwi>
+ #include <../lx2162asom_rev2/include/common_pbi.rcwi>
+ #include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#endif
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw
+index 4724239..ba1f0d0 100644
+--- a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_7_0_auto.rcw
+@@ -23,3 +23,9 @@
+ #include <../lx2160acex7/include/SD3_0.rcwi>
+ #include <../lx2162asom_rev2/include/common_pbi.rcwi>
+ #include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#endif
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw
+index 3a7703d..7738294 100644
+--- a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_18_9_0_auto.rcw
+@@ -23,3 +23,9 @@
+ #include <../lx2160acex7/include/SD3_0.rcwi>
+ #include <../lx2162asom_rev2/include/common_pbi.rcwi>
+ #include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 18 == 18 || 18 == -18
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#endif
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_11_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_11_0_auto.rcw
+index 6a1863d..b4383a5 100644
+--- a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_11_0_auto.rcw
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_11_0_auto.rcw
+@@ -23,3 +23,9 @@
+ #include <../lx2160acex7/include/SD3_0.rcwi>
+ #include <../lx2162asom_rev2/include/common_pbi.rcwi>
+ #include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 2 == 18 || 2 == -18
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#endif
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_7_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_7_0_auto.rcw
+index 24cf24a..10feef7 100644
+--- a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_7_0_auto.rcw
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_7_0_auto.rcw
+@@ -23,3 +23,9 @@
+ #include <../lx2160acex7/include/SD3_0.rcwi>
+ #include <../lx2162asom_rev2/include/common_pbi.rcwi>
+ #include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 2 == 18 || 2 == -18
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#endif
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_9_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_9_0_auto.rcw
+index 9533815..7c8e6d9 100644
+--- a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_9_0_auto.rcw
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_9_0_auto.rcw
+@@ -23,3 +23,9 @@
+ #include <../lx2160acex7/include/SD3_0.rcwi>
+ #include <../lx2162asom_rev2/include/common_pbi.rcwi>
+ #include <../lx2160acex7/include/bootlocptr.rcwi>
++
++#if 2 == 18 || 2 == -18
++/* set default serdes lane equalization parameters for 25G */
++#include <../lx2160asi/25g_eq_s1_lane_e.rcw>
++#include <../lx2160asi/25g_eq_s1_lane_f.rcw>
++#endif
+diff --git a/lx2162asom_rev2/include/common_pbi.rcwi b/lx2162asom_rev2/include/common_pbi.rcwi
+index b313c1e..c917829 100644
+--- a/lx2162asom_rev2/include/common_pbi.rcwi
++++ b/lx2162asom_rev2/include/common_pbi.rcwi
+@@ -25,6 +25,9 @@
+ /* SerDes Errata A-050479 */
+ #include <../lx2160asi/a050479.rcw>
+
++/* DPMAC7/8/9/10 clock disable (not available on LX2162) */
++#include <../lx2162aqds/disable_mac7_10.rcw>
++
+ /* PEX2/5/6 clock disable (not available on LX2162) */
+ #include <../lx2162aqds/disable_pci2_5_6.rcw>
+
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0001-pci-ls_pcie_g4-Wait-100ms-for-Link-Up-in-ls_pcie_g4_.patch b/board/solidrun/lx2160acex7/patches/uboot/0001-pci-ls_pcie_g4-Wait-100ms-for-Link-Up-in-ls_pcie_g4_.patch
new file mode 100644
index 0000000000..381fa9e0e3
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0001-pci-ls_pcie_g4-Wait-100ms-for-Link-Up-in-ls_pcie_g4_.patch
@@ -0,0 +1,66 @@
+From affb5ce1d897868b5b0df464dce8aa31dc741c84 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Wed, 3 Apr 2024 17:58:37 +0200
+Subject: [PATCH 01/14] pci: ls_pcie_g4: Wait 100ms for Link Up in
+ ls_pcie_g4_probe
+
+PCI Link-up can be delayed especially with pci bridges or fpga starting
+up slowly.
+
+Add a 100ms delay during probe polling for link-up.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ drivers/pci/pcie_layerscape_gen4.c | 21 ++++++++++++++++++++-
+ 1 file changed, 20 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
+index 021c975869f..2fbb507c628 100644
+--- a/drivers/pci/pcie_layerscape_gen4.c
++++ b/drivers/pci/pcie_layerscape_gen4.c
+@@ -19,6 +19,10 @@
+
+ #include "pcie_layerscape_gen4.h"
+
++#include <linux/delay.h>
++#define LINK_WAIT_RETRIES 100
++#define LINK_WAIT_TIMEOUT 1000
++
+ DECLARE_GLOBAL_DATA_PTR;
+
+ LIST_HEAD(ls_pcie_g4_list);
+@@ -50,6 +53,22 @@ static int ls_pcie_g4_link_up(struct ls_pcie_g4 *pcie)
+ return 1;
+ }
+
++static int ls_pcie_g4_wait_for_link(struct ls_pcie_g4 *pcie)
++{
++ int retries;
++
++ /* check if the link is up or not */
++ for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) {
++ if (ls_pcie_g4_link_up(pcie)) {
++ return 1;
++ }
++
++ udelay(LINK_WAIT_TIMEOUT);
++ }
++
++ return 0;
++}
++
+ static void ls_pcie_g4_ep_enable_cfg(struct ls_pcie_g4 *pcie)
+ {
+ ccsr_writel(pcie, GPEX_CFG_READY, PCIE_CONFIG_READY);
+@@ -548,7 +567,7 @@ static int ls_pcie_g4_probe(struct udevice *dev)
+ val |= PPIO_EN;
+ ccsr_writel(pcie, PAB_PEX_PIO_CTRL(0), val);
+
+- if (!ls_pcie_g4_link_up(pcie)) {
++ if (!ls_pcie_g4_wait_for_link(pcie)) {
+ /* Let the user know there's no PCIe link */
+ printf(": no link\n");
+ return 0;
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0002-pci-ls_pcie-Wait-100ms-for-Link-Up-in-ls_pcie_probe.patch b/board/solidrun/lx2160acex7/patches/uboot/0002-pci-ls_pcie-Wait-100ms-for-Link-Up-in-ls_pcie_probe.patch
new file mode 100644
index 0000000000..4efc23e6a9
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0002-pci-ls_pcie-Wait-100ms-for-Link-Up-in-ls_pcie_probe.patch
@@ -0,0 +1,65 @@
+From ad862f120ce4f6b0627cd1ea70a9de8b2f8a264c Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sun, 14 Apr 2024 16:45:42 +0200
+Subject: [PATCH 02/14] pci: ls_pcie: Wait 100ms for Link Up in ls_pcie_probe
+
+PCI Link-up can be delayed especially with pci bridges or fpga starting
+up slowly.
+
+Add a 100ms delay during probe polling for link-up.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ drivers/pci/pcie_layerscape_rc.c | 21 ++++++++++++++++++++-
+ 1 file changed, 20 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
+index 6a5bf88da23..33bd14ad81a 100644
+--- a/drivers/pci/pcie_layerscape_rc.c
++++ b/drivers/pci/pcie_layerscape_rc.c
+@@ -19,6 +19,10 @@
+ #endif
+ #include "pcie_layerscape.h"
+
++#include <linux/delay.h>
++#define LINK_WAIT_RETRIES 100
++#define LINK_WAIT_TIMEOUT 1000
++
+ DECLARE_GLOBAL_DATA_PTR;
+
+ struct ls_pcie_drvdata {
+@@ -27,6 +30,22 @@ struct ls_pcie_drvdata {
+ bool big_endian;
+ };
+
++static int ls_pcie_wait_for_link(struct ls_pcie *pcie)
++{
++ int retries;
++
++ /* check if the link is up or not */
++ for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) {
++ if (ls_pcie_link_up(pcie)) {
++ return 1;
++ }
++
++ udelay(LINK_WAIT_TIMEOUT);
++ }
++
++ return 0;
++}
++
+ static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
+ {
+ struct ls_pcie *pcie = pcie_rc->pcie;
+@@ -375,7 +394,7 @@ static int ls_pcie_probe(struct udevice *dev)
+ "Root Complex");
+ ls_pcie_setup_ctrl(pcie_rc);
+
+- if (!ls_pcie_link_up(pcie)) {
++ if (!ls_pcie_wait_for_link(pcie)) {
+ /* Let the user know there's no PCIe link */
+ printf(": no link\n");
+ return 0;
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0003-fsl-lsch3-update-calculation-of-ddr-clock-rate-to-in.patch b/board/solidrun/lx2160acex7/patches/uboot/0003-fsl-lsch3-update-calculation-of-ddr-clock-rate-to-in.patch
new file mode 100644
index 0000000000..eb04ef3de1
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0003-fsl-lsch3-update-calculation-of-ddr-clock-rate-to-in.patch
@@ -0,0 +1,63 @@
+From 991e3e98563aff0f980bb70b4bee205d2b597b45 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Tue, 8 Oct 2024 13:29:36 +0200
+Subject: [PATCH 03/14] fsl-lsch3: update calculation of ddr clock rate to
+ include divider
+
+DDR clock is passes through a divider and a multiplier - and is then
+again doubled once by the phy and once by the controller.
+The doubling was previously hidden by divider default value of 4.
+
+Take into account the divider value per MEM_PLL_CFG when calculating ddr
+bus frequency, and multiply the result by 4.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 8 ++++++++
+ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++++
+ 2 files changed, 12 insertions(+)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+index 137778dc136..04045839a27 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+@@ -92,11 +92,19 @@ void get_sys_info(struct sys_info *sys_info)
+ sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+ FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
+ FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
++ sys_info->freq_ddrbus /= ((gur_in32(&gur->rcwsr[0]) >>
++ FSL_CHASSIS3_RCWSR0_MEM_PLL_CFG_SHIFT) &
++ FSL_CHASSIS3_RCWSR0_MEM_PLL_CFG_MASK) + 1;
++ /* ddr clock is doubled at phy, then doubled again controller */
++ sys_info->freq_ddrbus *= 4;
+ #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+ if (soc_has_dp_ddr()) {
+ sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
+ FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
+ FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
++ sys_info->freq_ddrbus2 /= ((gur_in32(&gur->rcwsr[0]) >>
++ FSL_CHASSIS3_RCWSR0_MEM2_PLL_CFG_SHIFT) &
++ FSL_CHASSIS3_RCWSR0_MEM2_PLL_CFG_MASK) + 1;
+ } else {
+ sys_info->freq_ddrbus2 = 0;
+ }
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+index ca5e33379ba..968173480f4 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+@@ -375,8 +375,12 @@ struct ccsr_gur {
+
+ #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
+ #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
++#define FSL_CHASSIS3_RCWSR0_MEM_PLL_CFG_SHIFT 8
++#define FSL_CHASSIS3_RCWSR0_MEM_PLL_CFG_MASK 0x3
+ #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
+ #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
++#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_CFG_SHIFT 16
++#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_CFG_MASK 0x3
+ #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
+ #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
+
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0004-armv8-lx2160a-enable-workaround-for-SPI-erratum-A-05.patch b/board/solidrun/lx2160acex7/patches/uboot/0004-armv8-lx2160a-enable-workaround-for-SPI-erratum-A-05.patch
new file mode 100644
index 0000000000..b32f477d7b
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0004-armv8-lx2160a-enable-workaround-for-SPI-erratum-A-05.patch
@@ -0,0 +1,103 @@
+From 078a1018543d76c7e875abbd0fc9d041c8441529 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Thu, 24 Oct 2024 16:17:49 +0200
+Subject: [PATCH 04/14] armv8: lx2160a: enable workaround for SPI erratum
+ A-050752
+
+When RCW is loaded from SDHC1, chip-selects signals for SPI3 are always
+low and not usable.
+
+Implement workaround for erratum A-050752 by clearing rcw source values
+in dynamic configuration register and masking HRESET_B.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++++
+ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +++
+ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 18 ++++++++++++++++++
+ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 ++++
+ 4 files changed, 29 insertions(+)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+index 27509fcca2c..6937d9f5b92 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
++++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+@@ -308,6 +308,7 @@ config ARCH_LX2160A
+ select SYS_FSL_EC2
+ select SYS_FSL_ERRATUM_A050204
+ select SYS_FSL_ERRATUM_A011334
++ select SYS_FSL_ERRATUM_A050752
+ select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
+ select SYS_FSL_HAS_RGMII
+ select SYS_FSL_HAS_SEC
+@@ -667,6 +668,9 @@ config SYS_FSL_ERRATUM_A009660
+ config SYS_FSL_ERRATUM_A050382
+ bool
+
++config SYS_FSL_ERRATUM_A050752
++ bool
++
+ config SYS_FSL_HAS_RGMII
+ bool
+ depends on SYS_FSL_EC1 || SYS_FSL_EC2
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+index 12d31184ad9..ac39f11e3b3 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+@@ -1128,6 +1128,9 @@ int arch_early_init_r(void)
+ #endif
+ #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
+ erratum_a009942_check_cpo();
++#endif
++#ifdef CONFIG_SYS_FSL_ERRATUM_A050752
++ erratum_a050752();
+ #endif
+ if (check_psci()) {
+ debug("PSCI: PSCI does not exist.\n");
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+index 4c61d28c20f..d04f802967a 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+@@ -318,6 +318,24 @@ void erratum_a009635(void)
+ writel(val | 0x80000000, EPU_EPGCR);
+ }
+ #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
++#ifdef CONFIG_SYS_FSL_ERRATUM_A050752
++#define RESET_BASE 0x01e60000
++#define RESET_CCSR 0
++#define RESET_CCSR_HRESET_B_DIS BIT(25)
++
++void erratum_a050752(void)
++{
++ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
++ u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
++ u32 __iomem *reset_ccsr = (u32 __iomem *)RESET_BASE;
++ u32 val;
++
++ val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
++ val &= ~DCFG_PORSR1_RCW_SRC;
++ out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
++ out_le32(reset_ccsr + RESET_CCSR / 4, RESET_CCSR_HRESET_B_DIS);
++}
++#endif /* CONFIG_SYS_FSL_ERRATUM_A050752 */
+
+ static void erratum_rcw_src(void)
+ {
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+index bd41df1be44..3e7c5b0e724 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+@@ -131,6 +131,10 @@ void erratum_a009635(void);
+ void erratum_a010315(void);
+ #endif
+
++#ifdef CONFIG_SYS_FSL_ERRATUM_A050752
++void erratum_a050752(void);
++#endif
++
+ bool soc_has_dp_ddr(void);
+ bool soc_has_aiop(void);
+
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0005-cmd-tlv_eeprom-don-t-fail-boot-when-reading-eeprom-f.patch b/board/solidrun/lx2160acex7/patches/uboot/0005-cmd-tlv_eeprom-don-t-fail-boot-when-reading-eeprom-f.patch
new file mode 100644
index 0000000000..54c07a7a82
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0005-cmd-tlv_eeprom-don-t-fail-boot-when-reading-eeprom-f.patch
@@ -0,0 +1,32 @@
+From 8c327f3571ce41e546b2c9059785f6158a4222fb Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sat, 2 Nov 2024 16:31:01 +0100
+Subject: [PATCH 05/14] cmd: tlv_eeprom: don't fail boot when reading eeprom
+ fails
+
+When u-boot calls mac_read_from_eeprom during init an error return code
+will fail the boot before reaching u-boot shell.
+
+Return success error code even on error, mac addresses are not critical.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ cmd/tlv_eeprom.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
+index 57cfd355df1..b178c23d394 100644
+--- a/cmd/tlv_eeprom.c
++++ b/cmd/tlv_eeprom.c
+@@ -1037,7 +1037,7 @@ int mac_read_from_eeprom(void)
+
+ if (read_eeprom(devnum, eeprom)) {
+ printf("Read failed.\n");
+- return -1;
++ return 0;
+ }
+
+ maccount = 1;
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0006-cmd-tlv_eeprom-support-specifying-tlv-eeprom-in-DT-a.patch b/board/solidrun/lx2160acex7/patches/uboot/0006-cmd-tlv_eeprom-support-specifying-tlv-eeprom-in-DT-a.patch
new file mode 100644
index 0000000000..20c18c782a
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0006-cmd-tlv_eeprom-support-specifying-tlv-eeprom-in-DT-a.patch
@@ -0,0 +1,57 @@
+From 53600ad97598faf966eb5155f243b42e5a2c0ce5 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Mon, 4 Nov 2024 15:08:01 +0100
+Subject: [PATCH 06/14] cmd: tlv_eeprom: support specifying tlv eeprom in DT
+ alias tlv[0-255]
+
+Systems might have many eeproms of which only some might be used for TLV
+data.
+If present, use aliases tlv0, tlv1, ... for finding tlv eeproms.
+
+If no eeproms are found by alias, fall back to current logic if using
+first eeproms in the system.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ cmd/tlv_eeprom.c | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
+index b178c23d394..27eb4e3488a 100644
+--- a/cmd/tlv_eeprom.c
++++ b/cmd/tlv_eeprom.c
+@@ -912,9 +912,31 @@ static void show_tlv_devices(int current_dev)
+ static int find_tlv_devices(struct udevice **tlv_devices_p)
+ {
+ int ret;
++ char alias_name[7];
+ int count_dev = 0;
++ ofnode node;
+ struct udevice *dev;
+
++ /* find by alias */
++ for (int i = 0; i < MAX_TLV_DEVICES; i++) {
++ snprintf(alias_name, sizeof(alias_name), "tlv%d", i);
++ node = ofnode_get_aliases_node(alias_name);
++ if (!ofnode_valid(node))
++ continue;
++
++ ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev);
++ if (ret) {
++ debug("get device \"%s\" failed with %d\n", alias_name, ret);
++ continue;
++ }
++
++ tlv_devices_p[i] = dev;
++ count_dev++;
++ }
++ if (count_dev)
++ return 0;
++
++ /* fall-back: find among all eeproms */
+ for (ret = uclass_first_device_check(UCLASS_I2C_EEPROM, &dev);
+ dev;
+ ret = uclass_next_device_check(&dev)) {
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0007-gpio-mpc8xxx-fix-build-on-layerscape-arch.patch b/board/solidrun/lx2160acex7/patches/uboot/0007-gpio-mpc8xxx-fix-build-on-layerscape-arch.patch
new file mode 100644
index 0000000000..07aa9783e8
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0007-gpio-mpc8xxx-fix-build-on-layerscape-arch.patch
@@ -0,0 +1,29 @@
+From 5e3071d8030e57b82207c0c81e9d73204de0a10d Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Tue, 29 Jul 2025 11:09:55 +0200
+Subject: [PATCH 07/14] gpio: mpc8xxx: fix build on layerscape arch
+
+asm/gpio.h include does not pull in the arch-specific gpio header for
+layerscape - include it explicitly for now (likely breaking powerpc
+platforms)
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ drivers/gpio/mpc8xxx_gpio.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
+index f7ffd8926ad..e30d434ae82 100644
+--- a/drivers/gpio/mpc8xxx_gpio.c
++++ b/drivers/gpio/mpc8xxx_gpio.c
+@@ -13,6 +13,7 @@
+ #include <dm.h>
+ #include <mapmem.h>
+ #include <asm/gpio.h>
++#include <asm/arch-fsl-layerscape/gpio.h>
+ #include <asm/io.h>
+ #include <dm/of_access.h>
+
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0008-arch-arm-dts-fsl-lx2160a.dtsi-add-pcs-phys.patch b/board/solidrun/lx2160acex7/patches/uboot/0008-arch-arm-dts-fsl-lx2160a.dtsi-add-pcs-phys.patch
new file mode 100644
index 0000000000..999dec9ebc
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0008-arch-arm-dts-fsl-lx2160a.dtsi-add-pcs-phys.patch
@@ -0,0 +1,386 @@
+From f37a22f89c8c09f9f9d5dcbcf5dce431b955f574 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Fri, 8 Aug 2025 16:48:32 +0200
+Subject: [PATCH 08/14] arch: arm: dts: fsl-lx2160a.dtsi: add pcs phys
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ arch/arm/dts/fsl-lx2160a.dtsi | 253 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 253 insertions(+)
+
+diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
+index 680c69c7b73..4320a8d08bf 100644
+--- a/arch/arm/dts/fsl-lx2160a.dtsi
++++ b/arch/arm/dts/fsl-lx2160a.dtsi
+@@ -487,108 +487,126 @@
+ dpmac1: dpmac at 1 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x1>;
++ pcs-handle = <&pcs1>;
+ status = "disabled";
+ };
+
+ dpmac2: dpmac at 2 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x2>;
++ pcs-handle = <&pcs2>;
+ status = "disabled";
+ };
+
+ dpmac3: dpmac at 3 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x3>;
++ pcs-handle = <&pcs3>;
+ status = "disabled";
+ };
+
+ dpmac4: dpmac at 4 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x4>;
++ pcs-handle = <&pcs4>;
+ status = "disabled";
+ };
+
+ dpmac5: dpmac at 5 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x5>;
++ pcs-handle = <&pcs5>;
+ status = "disabled";
+ };
+
+ dpmac6: dpmac at 6 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x6>;
++ pcs-handle = <&pcs6>;
+ status = "disabled";
+ };
+
+ dpmac7: dpmac at 7 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x7>;
++ pcs-handle = <&pcs7>;
+ status = "disabled";
+ };
+
+ dpmac8: dpmac at 8 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x8>;
++ pcs-handle = <&pcs8>;
+ status = "disabled";
+ };
+
+ dpmac9: dpmac at 9 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x9>;
++ pcs-handle = <&pcs9>;
+ status = "disabled";
+ };
+
+ dpmac10: dpmac at a {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xa>;
++ pcs-handle = <&pcs10>;
+ status = "disabled";
+ };
+
+ dpmac11: dpmac at b {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xb>;
++ pcs-handle = <&pcs11>;
+ status = "disabled";
+ };
+
+ dpmac12: dpmac at c {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xc>;
++ pcs-handle = <&pcs12>;
+ status = "disabled";
+ };
+
+ dpmac13: dpmac at d {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xd>;
++ pcs-handle = <&pcs13>;
+ status = "disabled";
+ };
+
+ dpmac14: dpmac at e {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xe>;
++ pcs-handle = <&pcs14>;
+ status = "disabled";
+ };
+
+ dpmac15: dpmac at f {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xf>;
++ pcs-handle = <&pcs15>;
+ status = "disabled";
+ };
+
+ dpmac16: dpmac at 10 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x10>;
++ pcs-handle = <&pcs16>;
+ status = "disabled";
+ };
+
+ dpmac17: dpmac at 11 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x11>;
++ pcs-handle = <&pcs17>;
+ status = "disabled";
+ };
+
+ dpmac18: dpmac at 12 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x12>;
++ pcs-handle = <&pcs18>;
+ status = "disabled";
+ };
+ };
+@@ -613,6 +631,241 @@
+ #size-cells = <0>;
+ status = "disabled";
+ };
++
++ pcs_mdio1: mdio at 8c07000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c07000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs1: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio2: mdio at 8c0b000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c0b000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs2: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio3: mdio at 8c0f000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c0f000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs3: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio4: mdio at 8c13000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c13000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs4: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio5: mdio at 8c17000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c17000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs5: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio6: mdio at 8c1b000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c1b000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs6: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio7: mdio at 8c1f000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c1f000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs7: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio8: mdio at 8c23000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c23000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs8: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio9: mdio at 8c27000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c27000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs9: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio10: mdio at 8c2b000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c2b000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs10: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio11: mdio at 8c2f000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c2f000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs11: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio12: mdio at 8c33000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c33000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs12: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio13: mdio at 8c37000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c37000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs13: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio14: mdio at 8c3b000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c3b000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs14: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio15: mdio at 8c3f000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c3f000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs15: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio16: mdio at 8c43000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c43000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs16: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio17: mdio at 8c47000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c47000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs17: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
++ pcs_mdio18: mdio at 8c4b000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c4b000 0x0 0x1000>;
++ little-endian;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pcs18: ethernet-phy at 0 {
++ reg = <0>;
++ };
++ };
++
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0009-arch-arm-dts-fsl-lx2160a.dtsi-add-psci-node.patch b/board/solidrun/lx2160acex7/patches/uboot/0009-arch-arm-dts-fsl-lx2160a.dtsi-add-psci-node.patch
new file mode 100644
index 0000000000..083b79053e
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0009-arch-arm-dts-fsl-lx2160a.dtsi-add-psci-node.patch
@@ -0,0 +1,30 @@
+From c45ae8075ca32d9dd815f769e8ab0dc6b293360b Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Fri, 8 Aug 2025 13:59:05 +0200
+Subject: [PATCH 09/14] arch: arm: dts: fsl-lx2160a.dtsi: add psci node
+
+LX2160A uses arm-trusted-firmware as first stage loader implementing
+psci. Add description for the psci functionality.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ arch/arm/dts/fsl-lx2160a.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
+index 4320a8d08bf..70f5287ad58 100644
+--- a/arch/arm/dts/fsl-lx2160a.dtsi
++++ b/arch/arm/dts/fsl-lx2160a.dtsi
+@@ -872,4 +872,9 @@
+ method = "smc";
+ };
+ };
++
++ psci {
++ compatible = "arm,psci-0.2";
++ method = "smc";
++ };
+ };
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0010-net-phy-marvell10g-add-support-for-88e2580-phy.patch b/board/solidrun/lx2160acex7/patches/uboot/0010-net-phy-marvell10g-add-support-for-88e2580-phy.patch
new file mode 100644
index 0000000000..148e1f6e2c
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0010-net-phy-marvell10g-add-support-for-88e2580-phy.patch
@@ -0,0 +1,43 @@
+From a88cc54f83c53735d908daf77166214fd03a25c6 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Fri, 8 Aug 2025 16:49:33 +0200
+Subject: [PATCH 10/14] net: phy: marvell10g: add support for 88e2580 phy
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ drivers/net/phy/marvell10g.c | 9 +++++++++
+ include/marvell_phy.h | 1 +
+ 2 files changed, 10 insertions(+)
+
+diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
+index 9e64672f5ca..f5d8d18d10f 100644
+--- a/drivers/net/phy/marvell10g.c
++++ b/drivers/net/phy/marvell10g.c
+@@ -603,3 +603,12 @@ U_BOOT_PHY_DRIVER(mv88e2110_mv88e2111) = {
+ .data = (ulong)&mv2110_mv2111_type,
+ .config = mv3310_config,
+ };
++
++U_BOOT_PHY_DRIVER(mv88e2580) = {
++ .name = "mv88e2580",
++ .uid = MARVELL_PHY_ID_88E2580,
++ .mask = MARVELL_PHY_ID_MASK,
++ .features = PHY_10G_FEATURES,
++ .data = (ulong)&mv3310_mv3340_type,
++ .config = mv3310_config,
++};
+diff --git a/include/marvell_phy.h b/include/marvell_phy.h
+index 0f06c2287b5..8fab10be087 100644
+--- a/include/marvell_phy.h
++++ b/include/marvell_phy.h
+@@ -25,6 +25,7 @@
+ #define MARVELL_PHY_ID_88X3310 0x002b09a0
+ #define MARVELL_PHY_ID_88E2110 0x002b09b0
+ #define MARVELL_PHY_ID_88X2222 0x01410f10
++#define MARVELL_PHY_ID_88E2580 0x002b0bc3
+
+ /* Marvel 88E1111 in Finisar SFP module with modified PHY ID */
+ #define MARVELL_PHY_ID_88E1111_FINISAR 0x01ff0cc0
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0011-add-solidrun-lx2160-cex7-board-support.patch b/board/solidrun/lx2160acex7/patches/uboot/0011-add-solidrun-lx2160-cex7-board-support.patch
new file mode 100644
index 0000000000..1aabae8c71
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0011-add-solidrun-lx2160-cex7-board-support.patch
@@ -0,0 +1,1753 @@
+From 11c1b62e4f9c7ca0f4b3574353c1537c3b3d9cb6 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Thu, 13 Jun 2024 17:26:47 +0200
+Subject: [PATCH 11/14] add solidrun lx2160-cex7 board support
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ arch/arm/Kconfig | 14 +
+ arch/arm/dts/Makefile | 1 +
+ arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi | 36 ++
+ arch/arm/dts/fsl-lx2160a-cex7.dts | 17 +
+ arch/arm/dts/fsl-lx2160a-cex7.dtsi | 184 +++++++
+ board/solidrun/lx2160acex7/Kconfig | 15 +
+ board/solidrun/lx2160acex7/Makefile | 11 +
+ board/solidrun/lx2160acex7/ddr.c | 22 +
+ board/solidrun/lx2160acex7/eth_lx2160acex7.c | 45 ++
+ board/solidrun/lx2160acex7/lx2160a.c | 269 +++++++++
+ board/solidrun/lx2160acex7/serdes.c | 512 ++++++++++++++++++
+ configs/lx2160acex7_tfa_SECURE_BOOT_defconfig | 97 ++++
+ configs/lx2160acex7_tfa_defconfig | 109 ++++
+ include/configs/lx2160acex7.h | 282 ++++++++++
+ 14 files changed, 1614 insertions(+)
+ create mode 100644 arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi
+ create mode 100644 arch/arm/dts/fsl-lx2160a-cex7.dts
+ create mode 100644 arch/arm/dts/fsl-lx2160a-cex7.dtsi
+ create mode 100644 board/solidrun/lx2160acex7/Kconfig
+ create mode 100644 board/solidrun/lx2160acex7/Makefile
+ create mode 100644 board/solidrun/lx2160acex7/ddr.c
+ create mode 100644 board/solidrun/lx2160acex7/eth_lx2160acex7.c
+ create mode 100644 board/solidrun/lx2160acex7/lx2160a.c
+ create mode 100644 board/solidrun/lx2160acex7/serdes.c
+ create mode 100644 configs/lx2160acex7_tfa_SECURE_BOOT_defconfig
+ create mode 100644 configs/lx2160acex7_tfa_defconfig
+ create mode 100644 include/configs/lx2160acex7.h
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index eaf2c5d3df7..786d05d8d0c 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1462,6 +1462,19 @@ config TARGET_LS2081ARDB
+ development platform that supports the QorIQ LS2081A/LS2041A
+ Layerscape Architecture processor.
+
++config TARGET_LX2160ACEX7
++ bool "Support lx2160acex7"
++ select ARCH_LX2160A
++ select ARM64
++ select ARMV8_MULTIENTRY
++ select ARCH_SUPPORT_TFABOOT
++ select BOARD_LATE_INIT
++ help
++ Support for SolidRun LX2160ACEX7 platform.
++ The lx2160acex7 (LX2160A COM-Express Type 7)
++ is a high-performance platform based on the
++ QorIQ LX2160A Layerscape Architecture processor.
++
+ config TARGET_LX2160ARDB
+ bool "Support lx2160ardb"
+ select ARCH_LX2160A
+@@ -2371,6 +2384,7 @@ source "board/samsung/common/Kconfig"
+ source "board/siemens/common/Kconfig"
+ source "board/seeed/npi_imx6ull/Kconfig"
+ source "board/socionext/developerbox/Kconfig"
++source "board/solidrun/lx2160acex7/Kconfig"
+ source "board/st/stv0991/Kconfig"
+ source "board/tcl/sl50/Kconfig"
+ source "board/traverse/ten64/Kconfig"
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 737e959a6b5..e12136af4ab 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -598,6 +598,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+ fsl-ls1028a-rdb.dtb \
+ fsl-ls1028a-qds-duart.dtb \
+ fsl-ls1028a-qds-lpuart.dtb \
++ fsl-lx2160a-cex7.dtb \
+ fsl-lx2160a-rdb.dtb \
+ fsl-lx2160a-qds.dtb \
+ fsl-lx2160a-qds-3-x-x.dtb \
+diff --git a/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi b/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi
+new file mode 100644
+index 00000000000..9394c36d70e
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi
+@@ -0,0 +1,36 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++ aliases {
++ tlv0 = &{/i2c at 2000000/i2c-mux at 77/i2c at 0/eeprom at 57};
++ serial0 = &uart0;
++ };
++};
++
++&gpio2 {
++ /*
++ * AMC6821 THERM signal uses open-drain logic and can be driven
++ * by either the host (force full-speed) or the chip
++ * (thermal warning). Firmware drives it low during reset.
++ *
++ * Force fan full-speed while bootloader is active.
++ * TODO: Add fan-controller driver.
++ */
++ fan-full-speed-hog {
++ gpio-hog;
++ gpios = <2 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
++ output-high;
++ line-name = "fan-full-speed";
++ };
++};
++
++&{/i2c at 2000000/i2c-mux at 77/i2c at 1/fan-temperature-ctrlr at 18} {
++ /*u-boot does not currently have a driver for this fan-controller */
++ status = "disabled";
++};
++
++&uart0 {
++ status = "okay";
++};
+diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts
+new file mode 100644
+index 00000000000..3816034e279
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-cex7.dts
+@@ -0,0 +1,17 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/*
++ * Device Tree file for LX2160A-CEx7 Standalone (Generic Carrier Board)
++ *
++ * Copyright 2024 Josua Mayer <josua at solid-run.com>
++ */
++
++#include "fsl-lx2160a-cex7.dtsi"
++
++/* for SD-Card Boot */
++&esdhc0 {
++ sd-uhs-sdr104;
++ sd-uhs-sdr50;
++ sd-uhs-sdr25;
++ sd-uhs-sdr12;
++ status = "okay";
++};
+diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dtsi b/arch/arm/dts/fsl-lx2160a-cex7.dtsi
+new file mode 100644
+index 00000000000..e4b72707081
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-cex7.dtsi
+@@ -0,0 +1,184 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Device Tree file for LX2160A-CEx7
++//
++// Copyright 2019 SolidRun Ltd.
++
++/dts-v1/;
++
++#include "fsl-lx2160a.dtsi"
++
++/ {
++ model = "SolidRun LX2160A COM Express Type 7 module";
++ compatible = "solidrun,lx2160a-cex7", "fsl,lx2160a";
++
++ aliases {
++ crypto = &crypto;
++ };
++
++ sb_3v3: regulator-sb3v3 {
++ compatible = "regulator-fixed";
++ regulator-name = "RT7290";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++};
++
++&crypto {
++ status = "okay";
++};
++
++&dpmac17 {
++ phy-handle = <&rgmii_phy1>;
++ phy-connection-type = "rgmii-id";
++};
++
++&emdio1 {
++ status = "okay";
++
++ rgmii_phy1: ethernet-phy at 1 {
++ reg = <1>;
++ qca,smarteee-tw-us-1g = <24>;
++ };
++};
++
++&esdhc1 {
++ mmc-hs200-1_8v;
++ mmc-hs400-1_8v;
++ bus-width = <8>;
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++
++ i2c-mux at 77 {
++ compatible = "nxp,pca9547";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x77>;
++
++ i2c at 0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++
++ eeprom at 50 {
++ compatible = "atmel,24c512";
++ reg = <0x50>;
++ };
++
++ eeprom at 51 {
++ compatible = "atmel,spd";
++ reg = <0x51>;
++ };
++
++ eeprom at 53 {
++ compatible = "atmel,spd";
++ reg = <0x53>;
++ };
++
++ eeprom at 57 {
++ compatible = "atmel,24c02";
++ reg = <0x57>;
++ };
++ };
++
++ i2c at 1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++
++ fan-temperature-ctrlr at 18 {
++ compatible = "ti,amc6821";
++ reg = <0x18>;
++ };
++ };
++
++ i2c at 2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++
++ regulator at 5c {
++ compatible = "lltc,ltc3882";
++ reg = <0x5c>;
++ };
++ };
++
++ i2c at 3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++
++ temperature-sensor at 48 {
++ compatible = "nxp,sa56004";
++ reg = <0x48>;
++ vcc-supply = <&sb_3v3>;
++ };
++ };
++
++ sfp0_i2c: i2c at 4 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <4>;
++ };
++
++ sfp1_i2c: i2c at 5 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <5>;
++ };
++
++ sfp2_i2c: i2c at 6 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <6>;
++ };
++
++ sfp3_i2c: i2c at 7 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <7>;
++ };
++ };
++};
++
++&i2c2 {
++ status = "okay";
++};
++
++&i2c4 {
++ status = "okay";
++
++ rtc at 51 {
++ compatible = "nxp,pcf2129";
++ reg = <0x51>;
++ };
++};
++
++&fspi {
++ status = "okay";
++
++ flash at 0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "micron,m25p80";
++ m25p,fast-read;
++ spi-max-frequency = <50000000>;
++ reg = <0>;
++ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
++ spi-rx-bus-width = <8>;
++ spi-tx-bus-width = <1>;
++ };
++};
++
++&usb0 {
++ status = "okay";
++};
++
++&usb1 {
++ status = "okay";
++};
+diff --git a/board/solidrun/lx2160acex7/Kconfig b/board/solidrun/lx2160acex7/Kconfig
+new file mode 100644
+index 00000000000..85673846a4a
+--- /dev/null
++++ b/board/solidrun/lx2160acex7/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_LX2160ACEX7
++
++config SYS_BOARD
++ default "lx2160acex7"
++
++config SYS_VENDOR
++ default "solidrun"
++
++config SYS_SOC
++ default "fsl-layerscape"
++
++config SYS_CONFIG_NAME
++ default "lx2160acex7"
++
++endif
+diff --git a/board/solidrun/lx2160acex7/Makefile b/board/solidrun/lx2160acex7/Makefile
+new file mode 100644
+index 00000000000..a4bcd539cf8
+--- /dev/null
++++ b/board/solidrun/lx2160acex7/Makefile
+@@ -0,0 +1,11 @@
++#
++# Copyright 2018 Freescale Semiconductor
++# Copyright 2024 Josua Mayer <josua at solid-run.com>
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y += lx2160a.o
++obj-y += ddr.o
++obj-$(CONFIG_TARGET_LX2160ACEX7) += eth_lx2160acex7.o
++obj-y += serdes.o
+diff --git a/board/solidrun/lx2160acex7/ddr.c b/board/solidrun/lx2160acex7/ddr.c
+new file mode 100644
+index 00000000000..d872e575306
+--- /dev/null
++++ b/board/solidrun/lx2160acex7/ddr.c
+@@ -0,0 +1,22 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2018 NXP
++ * Copyright 2024 Josua Mayer <josua at solid-run.com>
++ */
++
++#include <common.h>
++#include <fsl_ddr_sdram.h>
++#include <fsl_ddr_dimm_params.h>
++#include <asm/global_data.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int fsl_initdram(void)
++{
++ gd->ram_size = tfa_get_dram_size();
++
++ if (!gd->ram_size)
++ gd->ram_size = fsl_ddr_sdram_size();
++
++ return 0;
++}
+diff --git a/board/solidrun/lx2160acex7/eth_lx2160acex7.c b/board/solidrun/lx2160acex7/eth_lx2160acex7.c
+new file mode 100644
+index 00000000000..bc7ae231c58
+--- /dev/null
++++ b/board/solidrun/lx2160acex7/eth_lx2160acex7.c
+@@ -0,0 +1,45 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2018-2021 NXP
++ *
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <command.h>
++#include <fm_eth.h>
++#include <fsl_mdio.h>
++#include <fsl-mc/fsl_mc.h>
++#include <fsl-mc/ldpaa_wriop.h>
++#include <netdev.h>
++#include <asm/arch/clock.h>
++#include <fdt_support.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int board_eth_init(struct bd_info *bis)
++{
++ return pci_eth_init(bis);
++}
++
++#if defined(CONFIG_RESET_PHY_R)
++void reset_phy(void)
++{
++#if defined(CONFIG_FSL_MC_ENET)
++ mc_env_boot();
++#endif
++}
++#endif /* CONFIG_RESET_PHY_R */
++
++#ifndef CONFIG_CMD_TLV_EEPROM
++int mac_read_from_eeprom(void)
++{
++ return 0;
++}
++#endif
++
++int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
++{
++ puts("Not implemented.\n");
++ return CMD_RET_FAILURE;
++}
+diff --git a/board/solidrun/lx2160acex7/lx2160a.c b/board/solidrun/lx2160acex7/lx2160a.c
+new file mode 100644
+index 00000000000..632fbff52dc
+--- /dev/null
++++ b/board/solidrun/lx2160acex7/lx2160a.c
+@@ -0,0 +1,269 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2018-2021 NXP
++ * Copyright 2024 Josua Mayer <josua at solid-run.com>
++ */
++
++#include <common.h>
++#include <asm/arch/clock.h>
++#include <asm/arch-fsl-layerscape/fsl_icid.h>
++#include <asm/arch/soc.h>
++#include <asm/gpio.h>
++#include <clock_legacy.h>
++#include <display_options.h>
++#include <dm.h>
++#include <dm/platform_data/serial_pl01x.h>
++#include <fdt_support.h>
++#include <fsl-mc/fsl_mc.h>
++#include <fsl_ddr.h>
++#include <init.h>
++#include <malloc.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int board_early_init_f(void)
++{
++ fsl_lsch3_early_init_f();
++ return 0;
++}
++
++#ifdef CONFIG_OF_BOARD_FIXUP
++void board_fix_fdt_eth(void *fdt, u32 srds_s1, u32 srds_s2, u32 is_lx2162);
++void board_fix_fdt_serdes_ports(void *fdt);
++
++static void board_fix_fdt_pci_silicon(void *fdt) {
++ char *reg_names, *reg_name;
++ int names_len, old_name_len, new_name_len, remaining_names_len;
++ struct str_map {
++ char *old_str;
++ char *new_str;
++ } reg_names_map[] = {
++ { "ccsr", "dbi" },
++ { "pf_ctrl", "ctrl" }
++ };
++ int off = -1, i = 0;
++
++ /* skip pci fixup on silicon version 1 */
++ if (IS_SVR_REV(get_svr(), 1, 0))
++ return;
++
++ /* fixup pci controller for silicon version 2 */
++ off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
++ while (off != -FDT_ERR_NOTFOUND) {
++ fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
++ strlen("fsl,ls-pcie") + 1);
++
++ reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
++ &names_len);
++ if (!reg_names)
++ continue;
++
++ reg_name = reg_names;
++ remaining_names_len = names_len - (reg_name - reg_names);
++ i = 0;
++ while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
++ old_name_len = strlen(reg_names_map[i].old_str);
++ new_name_len = strlen(reg_names_map[i].new_str);
++ if (memcmp(reg_name, reg_names_map[i].old_str,
++ old_name_len) == 0) {
++ /* first only leave required bytes for new_str
++ * and copy rest of the string after it
++ */
++ memcpy(reg_name + new_name_len,
++ reg_name + old_name_len,
++ remaining_names_len - old_name_len);
++ /* Now copy new_str */
++ memcpy(reg_name, reg_names_map[i].new_str,
++ new_name_len);
++ names_len -= old_name_len;
++ names_len += new_name_len;
++ i++;
++ }
++
++ reg_name = memchr(reg_name, '\0', remaining_names_len);
++ if (!reg_name)
++ break;
++
++ reg_name += 1;
++
++ remaining_names_len = names_len -
++ (reg_name - reg_names);
++ }
++
++ fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
++ off = fdt_node_offset_by_compatible(fdt, off,
++ "fsl,lx2160a-pcie");
++ }
++}
++
++/* fdt fixup for u-boot itself */
++int board_fix_fdt(void *fdt)
++{
++ /* allocate space in case properties must be added */
++ fdt_increase_size(fdt, 512);
++
++ /* fix fdt */
++ board_fix_fdt_serdes_ports(fdt);
++ board_fix_fdt_pci_silicon(fdt);
++
++ return 0;
++}
++#endif
++
++int checkboard(void)
++{
++ enum boot_src src = get_boot_src();
++ char buf[64];
++
++ cpu_name(buf);
++
++ puts("Boot Source: ");
++ if (src == BOOT_SOURCE_SD_MMC) {
++ puts("SD\n");
++ } else if (src == BOOT_SOURCE_SD_MMC2) {
++ puts("eMMC\n");
++ } else if (src == BOOT_SOURCE_XSPI_NOR) {
++ puts("FlexSPI\n");
++ } else {
++ puts("Unknown\n");
++ }
++
++ return 0;
++}
++
++unsigned long get_board_sys_clk(void)
++{
++ return 100000000;
++}
++
++unsigned long get_board_ddr_clk(void)
++{
++ return 100000000;
++}
++
++int board_init(void)
++{
++#if !defined(CONFIG_SYS_EARLY_PCI_INIT)
++ pci_init();
++#endif
++
++ return 0;
++}
++
++#ifdef CONFIG_BOARD_LATE_INIT
++int fsl_board_late_init(void) {
++ /* TODO: configure fan-controller here and release gpio-hog */
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_FSL_MC_ENET
++void fdt_fixup_board_enet(void *fdt)
++{
++ int offset;
++
++ /* mainline linux has fsl-mc below soc node */
++ offset = fdt_path_offset(fdt, "/soc/fsl-mc");
++
++ if (offset < 0)
++ /* older versions had fsl-mc at root level */
++ offset = fdt_path_offset(fdt, "/fsl-mc");
++
++ if (offset < 0) {
++ printf("%s: fsl-mc node not found in device tree (error %d)\n",
++ __func__, offset);
++ return;
++ }
++
++ if (get_mc_boot_status() == 0 &&
++ (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
++ fdt_status_okay(fdt, offset);
++ } else {
++ /* mc startup failed, disable in dtb */
++ fdt_status_fail(fdt, offset);
++ }
++}
++
++void board_quiesce_devices(void)
++{
++ fsl_mc_ldpaa_exit(gd->bd);
++}
++#endif
++
++#ifdef CONFIG_OF_BOARD_SETUP
++int ft_board_setup(void *blob, struct bd_info *bd)
++{
++ int i;
++ u16 mc_memory_bank = 0;
++
++ u64 *base;
++ u64 *size;
++ u64 mc_memory_base = 0;
++ u64 mc_memory_size = 0;
++ u16 total_memory_banks;
++ int err;
++
++ err = fdt_increase_size(blob, 512);
++ if (err) {
++ printf("%s fdt_increase_size: err=%s\n", __func__,
++ fdt_strerror(err));
++ return err;
++ }
++
++ ft_cpu_setup(blob, bd);
++
++ fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
++
++ if (mc_memory_base != 0)
++ mc_memory_bank++;
++
++ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
++
++ base = calloc(total_memory_banks, sizeof(u64));
++ size = calloc(total_memory_banks, sizeof(u64));
++
++ /* fixup DT for the three GPP DDR banks */
++ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
++ base[i] = gd->bd->bi_dram[i].start;
++ size[i] = gd->bd->bi_dram[i].size;
++ }
++
++#ifdef CONFIG_RESV_RAM
++ /* reduce size if reserved memory is within this bank */
++ if (gd->arch.resv_ram >= base[0] &&
++ gd->arch.resv_ram < base[0] + size[0])
++ size[0] = gd->arch.resv_ram - base[0];
++ else if (gd->arch.resv_ram >= base[1] &&
++ gd->arch.resv_ram < base[1] + size[1])
++ size[1] = gd->arch.resv_ram - base[1];
++ else if (gd->arch.resv_ram >= base[2] &&
++ gd->arch.resv_ram < base[2] + size[2])
++ size[2] = gd->arch.resv_ram - base[2];
++#endif
++
++ if (mc_memory_base != 0) {
++ for (i = 0; i <= total_memory_banks; i++) {
++ if (base[i] == 0 && size[i] == 0) {
++ base[i] = mc_memory_base;
++ size[i] = mc_memory_size;
++ break;
++ }
++ }
++ }
++
++ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
++
++#ifdef CONFIG_USB_HOST
++ fsl_fdt_fixup_dr_usb(blob, bd);
++#endif
++
++#ifdef CONFIG_FSL_MC_ENET
++ fdt_fsl_mc_fixup_iommu_map_entry(blob);
++ fdt_fixup_board_enet(blob);
++ fdt_reserve_mc_mem(blob, 0x4000);
++#endif
++ fdt_fixup_icid(blob);
++
++ return 0;
++}
++#endif
+diff --git a/board/solidrun/lx2160acex7/serdes.c b/board/solidrun/lx2160acex7/serdes.c
+new file mode 100644
+index 00000000000..c6b6d9bbfdc
+--- /dev/null
++++ b/board/solidrun/lx2160acex7/serdes.c
+@@ -0,0 +1,512 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2025 Josua Mayer <josua at solid-run.com>
++ *
++ */
++
++#include <fdt_support.h>
++
++/* SerDes base address */
++#define LYNX_28G_SDn_BASE(block) ((void *)0x01EA0000 + (block) * 0x10000)
++
++/* Protocol Configuration Register 0 */
++#define LYNX_28G_PCC0 0x1080
++#define LYNX_28G_PCC0_PEXA_CFG GENMASK(30, 28)
++#define LYNX_28G_PCC0_PEXB_CFG GENMASK(26, 24)
++
++/* Protocol Configuration Register 2 */
++#define LYNX_28G_PCC2 0x1088
++#define LYNX_28G_PCC2_SATAA_CFG GENMASK(30, 28)
++#define LYNX_28G_PCC2_SATAB_CFG GENMASK(26, 24)
++#define LYNX_28G_PCC2_SATAC_CFG GENMASK(22, 20)
++#define LYNX_28G_PCC2_SATAD_CFG GENMASK(18, 16)
++
++/* Protocol Configuration Register 8 */
++#define LYNX_28G_PCC8 0x10A0
++#define LYNX_28G_PCC8_SGMIIA_CFG GENMASK(30, 28)
++#define LYNX_28G_PCC8_SGMIIB_CFG GENMASK(26, 24)
++#define LYNX_28G_PCC8_SGMIIC_CFG GENMASK(22, 20)
++#define LYNX_28G_PCC8_SGMIID_CFG GENMASK(18, 16)
++#define LYNX_28G_PCC8_SGMIIE_CFG GENMASK(14, 12)
++#define LYNX_28G_PCC8_SGMIIF_CFG GENMASK(10, 8)
++#define LYNX_28G_PCC8_SGMIIG_CFG GENMASK(6, 4)
++#define LYNX_28G_PCC8_SGMIIH_CFG GENMASK(2, 0)
++
++/* Protocol Configuration Register C */
++#define LYNX_28G_PCCC 0x10B0
++#define LYNX_28G_PCCC_SXGMIIA_CFG GENMASK(30, 28)
++#define LYNX_28G_PCCC_SXGMIIB_CFG GENMASK(26, 24)
++#define LYNX_28G_PCCC_SXGMIIC_CFG GENMASK(22, 20)
++#define LYNX_28G_PCCC_SXGMIID_CFG GENMASK(18, 16)
++#define LYNX_28G_PCCC_SXGMIIE_CFG GENMASK(14, 12)
++#define LYNX_28G_PCCC_SXGMIIF_CFG GENMASK(10, 8)
++#define LYNX_28G_PCCC_SXGMIIG_CFG GENMASK(6, 4)
++#define LYNX_28G_PCCC_SXGMIIH_CFG GENMASK(2, 0)
++
++/* Protocol Configuration Register D */
++#define LYNX_28G_PCCD 0x10B4
++#define LYNX_28G_PCCD_E25GA_CFG GENMASK(30, 28)
++#define LYNX_28G_PCCD_E25GB_CFG GENMASK(26, 24)
++#define LYNX_28G_PCCD_E25GC_CFG GENMASK(22, 20)
++#define LYNX_28G_PCCD_E25GD_CFG GENMASK(18, 16)
++#define LYNX_28G_PCCD_E25GE_CFG GENMASK(14, 12)
++#define LYNX_28G_PCCD_E25GF_CFG GENMASK(10, 8)
++#define LYNX_28G_PCCD_E25GG_CFG GENMASK(6, 4)
++#define LYNX_28G_PCCD_E25GH_CFG GENMASK(2, 0)
++
++/* Protocol Configuration Register E */
++#define LYNX_28G_PCCE 0x10B8
++#define LYNX_28G_PCCE_E40GA_CFG GENMASK(30, 28)
++#define LYNX_28G_PCCE_E40GB_CFG GENMASK(26, 24)
++#define LYNX_28G_PCCE_E50GA_CFG GENMASK(22, 20)
++#define LYNX_28G_PCCE_E50GB_CFG GENMASK(18, 16)
++#define LYNX_28G_PCCE_E100GA_CFG GENMASK(14, 12)
++#define LYNX_28G_PCCE_E100GB_CFG GENMASK(10, 8)
++
++/* Lane a General Control Register */
++#define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
++#define LYNX_28G_LNaGCR0_PORT_RST_LEFT BIT(17)
++#define LYNX_28G_LNaGCR0_PORT_LN0_B BIT(16)
++#define LYNX_28G_LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3)
++#define LYNX_28G_LNaGCR0_PROTO_SEL_PCI 0x0
++#define LYNX_28G_LNaGCR0_PROTO_SEL_SGMII 0x8
++#define LYNX_28G_LNaGCR0_PROTO_SEL_SATA 0x10
++#define LYNX_28G_LNaGCR0_PROTO_SEL_XFI 0x50
++#define LYNX_28G_LNaGCR0_PROTO_SEL_25G 0xD0
++
++/* Lane a Tx Reset Control Register */
++#define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
++#define LYNX_28G_LNaTRSTCTL_DIS BIT(24)
++
++/* Lane a Rx Reset Control Register */
++#define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
++#define LYNX_28G_LNaRRSTCTL_DIS BIT(24)
++
++/* Reset Control Word 27 (RO) */
++#define RCWSR27_R ((void *)0x01e00168)
++#define RCWSR27_EC1_PMUX_MASK 0x00000003
++#define RCWSR27_EC1_PMUX_WRIOP_MAC_17_RGMII 0x00000000
++#define RCWSR27_EC2_PMUX_MASK 0x0000000C
++#define RCWSR27_EC2_PMUX_WRIOP_MAC_18_RGMII 0x00000000
++
++enum {
++ DPMAC1 = 0,
++ DPMAC2,
++ DPMAC3,
++ DPMAC4,
++ DPMAC5,
++ DPMAC6,
++ DPMAC7,
++ DPMAC8,
++ DPMAC9,
++ DPMAC10,
++ DPMAC11,
++ DPMAC12,
++ DPMAC13,
++ DPMAC14,
++ DPMAC15,
++ DPMAC16,
++ DPMAC17,
++ DPMAC18,
++ DPMAC_MAX
++};
++
++#ifdef CONFIG_OF_BOARD_FIXUP
++
++/* fix mac nodes based on serdes protocol */
++static void board_fix_fdt_macs(void *fdt) {
++ struct mac_node {
++ const char *const path;
++ const char *status;
++ const char *mode;
++ } macs[DPMAC_MAX] = {
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at 1", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at 2", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at 3", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at 4", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at 5", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at 6", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at 7", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at 8", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at 9", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at a", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at b", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at c", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at d", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at e", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at f", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at 10", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at 11", "disabled" },
++ { "/fsl-mc at 80c000000/dpmacs/dpmac at 12", "disabled" },
++ };
++
++ struct {
++ const u32 __iomem *pcr;
++ const u32 pcr_ena_mask;
++ const char *const mode;
++ const unsigned int mac;
++ } ports[] = {
++ {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIA_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC3,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIB_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC4,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIC_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC5,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIID_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC6,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIE_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC7,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIF_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC8,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIG_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC9,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIH_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC10,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIA_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC3,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIB_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC4,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIC_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC5,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIID_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC6,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIE_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC7,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIF_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC8,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIG_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC9,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIH_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC10,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GA_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC3,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GB_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC4,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GC_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC5,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GD_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC6,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GE_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC7,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GF_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC8,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GG_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC9,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GH_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC10,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
++ .pcr_ena_mask = LYNX_28G_PCCE_E40GA_CFG,
++ .mode = "xlaui4",
++ .mac = DPMAC1,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
++ .pcr_ena_mask = LYNX_28G_PCCE_E40GB_CFG,
++ .mode = "xlaui4",
++ .mac = DPMAC2,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
++ .pcr_ena_mask = LYNX_28G_PCCE_E50GA_CFG,
++ .mode = "caui2",
++ .mac = DPMAC1,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
++ .pcr_ena_mask = LYNX_28G_PCCE_E50GB_CFG,
++ .mode = "caui2",
++ .mac = DPMAC2,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
++ .pcr_ena_mask = LYNX_28G_PCCE_E100GA_CFG,
++ .mode = "caui4",
++ .mac = DPMAC1,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
++ .pcr_ena_mask = LYNX_28G_PCCE_E100GB_CFG,
++ .mode = "caui4",
++ .mac = DPMAC2,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIA_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC18,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIB_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC17,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIC_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC16,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIID_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC15,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIE_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC14,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIF_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC13,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIG_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC12,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIH_CFG,
++ .mode = "sgmii",
++ .mac = DPMAC11,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIA_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC18,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIB_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC17,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIC_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC16,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIID_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC15,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIE_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC14,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIF_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC13,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIG_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC12,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIH_CFG,
++ .mode = "xgmii",
++ .mac = DPMAC11,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GA_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC18,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GB_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC17,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GC_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC16,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GD_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC15,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GE_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC14,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GF_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC13,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GG_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC12,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GH_CFG,
++ .mode = "25g-aui",
++ .mac = DPMAC11,
++ }
++ };
++
++ for (int i = 0; i < ARRAY_SIZE(ports); i++) {
++ if (*ports[i].pcr & ports[i].pcr_ena_mask) {
++ macs[ports[i].mac].status = "okay";
++ macs[ports[i].mac].mode = ports[i].mode;
++ }
++ }
++
++ /* workaround for dpmac17.18 rgmii ports */
++ {
++ const u32 __iomem *const rcwsr27 = RCWSR27_R;
++ if ((*rcwsr27 & RCWSR27_EC1_PMUX_MASK) == RCWSR27_EC1_PMUX_WRIOP_MAC_17_RGMII) {
++ macs[DPMAC17].status = "okay";
++ macs[DPMAC17].mode = "rgmii-id";
++ }
++ if ((*rcwsr27 & RCWSR27_EC2_PMUX_MASK) == RCWSR27_EC2_PMUX_WRIOP_MAC_18_RGMII) {
++ macs[DPMAC18].status = "okay";
++ macs[DPMAC18].mode = "rgmii-id";
++ }
++ }
++
++ for (int i = 0; i < ARRAY_SIZE(macs); i++) {
++ fdt_delprop(fdt, fdt_path_offset(fdt, macs[i].path), "phy-mode");
++ do_fixup_by_path_string(fdt, macs[i].path, "status", macs[i].status);
++ do_fixup_by_path_string(fdt, macs[i].path, "phy-connection-type", macs[i].mode);
++ }
++}
++
++static void board_fix_fdt_pci_sata(void *fdt) {
++ struct {
++ const u32 __iomem *pcr;
++ const u32 pcr_ena_mask;
++ const char *const path;
++ } ports[] = {
++ {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC0,
++ .pcr_ena_mask = LYNX_28G_PCC0_PEXA_CFG,
++ .path = "/pcie at 3400000",
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC0,
++ .pcr_ena_mask = LYNX_28G_PCC0_PEXB_CFG,
++ .path = "/pcie at 3500000",
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC0,
++ .pcr_ena_mask = LYNX_28G_PCC0_PEXA_CFG,
++ .path = "/pcie at 3600000",
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC0,
++ .pcr_ena_mask = LYNX_28G_PCC0_PEXB_CFG,
++ .path = "/pcie at 3700000",
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(2) + LYNX_28G_PCC0,
++ .pcr_ena_mask = LYNX_28G_PCC0_PEXA_CFG,
++ .path = "/pcie at 3800000",
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(2) + LYNX_28G_PCC0,
++ .pcr_ena_mask = LYNX_28G_PCC0_PEXB_CFG,
++ .path = "/pcie at 3900000",
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC2,
++ .pcr_ena_mask = LYNX_28G_PCC2_SATAA_CFG,
++ .path = "/sata at 3200000",
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC2,
++ .pcr_ena_mask = LYNX_28G_PCC2_SATAB_CFG,
++ .path = "/sata at 3210000",
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC2,
++ .pcr_ena_mask = LYNX_28G_PCC2_SATAC_CFG,
++ .path = "/sata at 3220000",
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC2,
++ .pcr_ena_mask = LYNX_28G_PCC2_SATAD_CFG,
++ .path = "/sata at 3230000",
++ },
++ };
++
++ for (int i = 0; i < ARRAY_SIZE(ports); i++) {
++ const char *status = "disabled";
++ if (*ports[i].pcr & ports[i].pcr_ena_mask)
++ status = "okay";
++
++ do_fixup_by_path_string(fdt, ports[i].path, "status", status);
++ }
++}
++
++void board_fix_fdt_serdes_ports(void *fdt) {
++ board_fix_fdt_pci_sata(fdt);
++ board_fix_fdt_macs(fdt);
++}
++
++#endif /* CONFIG_OF_BOARD_FIXUP */
+diff --git a/configs/lx2160acex7_tfa_SECURE_BOOT_defconfig b/configs/lx2160acex7_tfa_SECURE_BOOT_defconfig
+new file mode 100644
+index 00000000000..d55bdb24a4b
+--- /dev/null
++++ b/configs/lx2160acex7_tfa_SECURE_BOOT_defconfig
+@@ -0,0 +1,97 @@
++CONFIG_ARM=y
++CONFIG_SKIP_LOWLEVEL_INIT=y
++CONFIG_GIC_V3_ITS=y
++CONFIG_TARGET_LX2160ACEX7=y
++CONFIG_TFABOOT=y
++CONFIG_SYS_TEXT_BASE=0x82000000
++CONFIG_SYS_MALLOC_LEN=0x202000
++CONFIG_SYS_MALLOC_F_LEN=0x6000
++CONFIG_NR_DRAM_BANKS=3
++CONFIG_ENV_SIZE=0x2000
++CONFIG_NXP_ESBC=y
++CONFIG_DM_GPIO=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
++CONFIG_FSPI_AHB_EN_4BYTE=y
++CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
++CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
++CONFIG_AHCI=y
++CONFIG_OF_BOARD_FIXUP=y
++CONFIG_REMAKE_ELF=y
++CONFIG_MP=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_OF_BOARD_SETUP=y
++CONFIG_OF_STDOUT_VIA_ALIAS=y
++CONFIG_DYNAMIC_SYS_CLK_FREQ=y
++CONFIG_USE_BOOTARGS=y
++CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
++CONFIG_DEFAULT_FDT_FILE="freescale/fsl-lx2160a-clearfog-cx.dtb"
++CONFIG_MISC_INIT_R=y
++CONFIG_CMD_GREPENV=y
++CONFIG_CMD_EEPROM=y
++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
++CONFIG_CMD_DM=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_OPTEE_RPMB=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_WDT=y
++CONFIG_CMD_CACHE=y
++CONFIG_OF_CONTROL=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_DM=y
++CONFIG_SATA=y
++CONFIG_SATA_CEVA=y
++CONFIG_FSL_CAAM=y
++CONFIG_DYNAMIC_DDR_CLK_FREQ=y
++CONFIG_DDR_ECC=y
++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
++CONFIG_MPC8XXX_GPIO=y
++CONFIG_DM_I2C=y
++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
++CONFIG_SYS_I2C_EEPROM_ADDR=0x57
++CONFIG_SUPPORT_EMMC_RPMB=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_HS400_SUPPORT=y
++CONFIG_FSL_ESDHC=y
++CONFIG_MTD=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_STMICRO=y
++CONFIG_SPI_FLASH_MT35XU=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_PHYLIB=y
++CONFIG_PHY_ATHEROS=y
++CONFIG_DM_ETH=y
++CONFIG_DM_MDIO=y
++CONFIG_E1000=y
++CONFIG_MII=y
++CONFIG_FSL_LS_MDIO=y
++CONFIG_NVME_PCI=y
++CONFIG_PCI=y
++CONFIG_PCIE_LAYERSCAPE_RC=y
++CONFIG_PCIE_LAYERSCAPE_GEN4=y
++CONFIG_DM_RTC=y
++CONFIG_RTC_PCF2127=y
++CONFIG_DM_SCSI=y
++CONFIG_DM_SERIAL=y
++CONFIG_PL01X_SERIAL=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_FSL_DSPI=y
++CONFIG_NXP_FSPI=y
++CONFIG_TEE=y
++CONFIG_OPTEE=y
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_RSA=y
++CONFIG_SPL_RSA=y
++CONFIG_RSA_SOFTWARE_EXP=y
++CONFIG_WDT=y
++CONFIG_WDT_SBSA=y
++CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+new file mode 100644
+index 00000000000..016daa899c8
+--- /dev/null
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -0,0 +1,109 @@
++CONFIG_ARM=y
++CONFIG_SKIP_LOWLEVEL_INIT=y
++CONFIG_GIC_V3_ITS=y
++CONFIG_TARGET_LX2160ACEX7=y
++CONFIG_TFABOOT=y
++CONFIG_TEXT_BASE=0x82000000
++CONFIG_SYS_MALLOC_LEN=0x202000
++CONFIG_SYS_MALLOC_F_LEN=0x6000
++CONFIG_NR_DRAM_BANKS=3
++CONFIG_ENV_SIZE=0x2000
++CONFIG_ENV_OFFSET=0x500000
++CONFIG_ENV_SECT_SIZE=0x20000
++CONFIG_DM_GPIO=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
++CONFIG_FSPI_AHB_EN_4BYTE=y
++CONFIG_SYS_MONITOR_LEN=958464
++CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
++CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
++CONFIG_ENV_ADDR=0x20500000
++CONFIG_PCI=y
++CONFIG_AHCI=y
++CONFIG_OF_BOARD_FIXUP=y
++CONFIG_SYS_FSL_NUM_CC_PLLS=4
++CONFIG_REMAKE_ELF=y
++CONFIG_MP=y
++CONFIG_DYNAMIC_SYS_CLK_FREQ=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_BOOTDELAY=10
++CONFIG_OF_BOARD_SETUP=y
++CONFIG_OF_STDOUT_VIA_ALIAS=y
++CONFIG_USE_BOOTARGS=y
++CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
++CONFIG_DEFAULT_FDT_FILE="freescale/fsl-lx2160a-clearfog-cx.dtb"
++CONFIG_SYS_PBSIZE=532
++CONFIG_CMD_TLV_EEPROM=y
++CONFIG_CMD_GREPENV=y
++CONFIG_CMD_EEPROM=y
++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
++CONFIG_CMD_DM=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_OPTEE_RPMB=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_POWEROFF=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_WDT=y
++CONFIG_CMD_CACHE=y
++CONFIG_OF_CONTROL=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_ENV_IS_IN_SPI_FLASH=y
++CONFIG_USE_ETHPRIME=y
++CONFIG_ETHPRIME="DPMAC17 at rgmii-id"
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_SATA=y
++CONFIG_SATA_CEVA=y
++CONFIG_FSL_CAAM=y
++CONFIG_DYNAMIC_DDR_CLK_FREQ=y
++CONFIG_DDR_ECC=y
++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
++CONFIG_SYS_FSL_DDR_INTLV_256B=y
++CONFIG_MPC8XXX_GPIO=y
++CONFIG_DM_I2C=y
++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_MUX_PCA954x=y
++CONFIG_I2C_EEPROM=y
++CONFIG_SYS_I2C_EEPROM_ADDR=0x57
++CONFIG_SUPPORT_EMMC_RPMB=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_HS400_SUPPORT=y
++CONFIG_FSL_ESDHC=y
++CONFIG_MTD=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_STMICRO=y
++CONFIG_SPI_FLASH_MT35XU=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_PHYLIB=y
++CONFIG_PHY_AQUANTIA=y
++CONFIG_PHY_ATHEROS=y
++CONFIG_FSL_MEMAC=y
++CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
++CONFIG_DM_ETH_PHY=y
++CONFIG_E1000=y
++CONFIG_MII=y
++CONFIG_NVME_PCI=y
++CONFIG_PCIE_LAYERSCAPE_RC=y
++CONFIG_PCIE_LAYERSCAPE_GEN4=y
++CONFIG_DM_RTC=y
++CONFIG_RTC_PCF2127=y
++CONFIG_DM_SERIAL=y
++CONFIG_PL01X_SERIAL=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_FSL_DSPI=y
++CONFIG_NXP_FSPI=y
++CONFIG_TEE=y
++CONFIG_OPTEE=y
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_USB_MAX_CONTROLLER_COUNT=2
++CONFIG_WDT=y
++CONFIG_WDT_SBSA=y
++CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
+new file mode 100644
+index 00000000000..652cce98b66
+--- /dev/null
++++ b/include/configs/lx2160acex7.h
+@@ -0,0 +1,282 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2018-2022 NXP
++ * Copyright 2024-2025 Josua Mayer <josua at solid-run.com>
++ */
++
++#ifndef __CONFIG_LX2160ACEX7_H
++#define __CONFIG_LX2160ACEX7_H
++
++#include <asm/arch/stream_id_lsch3.h>
++#include <asm/arch/config.h>
++#include <asm/arch/soc.h>
++
++#define CFG_SYS_FLASH_BASE 0x20000000
++
++/* DDR */
++#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
++#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
++#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
++#define CFG_SYS_SDRAM_SIZE 0x200000000UL
++#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
++#define SPD_EEPROM_ADDRESS1 0x51
++#define SPD_EEPROM_ADDRESS2 0x52
++#define SPD_EEPROM_ADDRESS3 0x53
++#define SPD_EEPROM_ADDRESS4 0x54
++#define SPD_EEPROM_ADDRESS5 0x55
++#define SPD_EEPROM_ADDRESS6 0x56
++#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
++
++/* SMP Definitinos */
++#define CPU_RELEASE_ADDR secondary_boot_addr
++
++/* Generic Timer Definitions */
++/*
++ * This is not an accurate number. It is used in start.S. The frequency
++ * will be udpated later when get_bus_freq(0) is available.
++ */
++
++
++/* Serial Port */
++#define CFG_PL011_CLOCK (get_bus_freq(0) / 4)
++#define CFG_SYS_SERIAL0 0x21c0000
++#define CFG_SYS_SERIAL1 0x21d0000
++#define CFG_SYS_SERIAL2 0x21e0000
++#define CFG_SYS_SERIAL3 0x21f0000
++/*below might needs to be removed*/
++#define CFG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \
++ (void *)CFG_SYS_SERIAL1, \
++ (void *)CFG_SYS_SERIAL2, \
++ (void *)CFG_SYS_SERIAL3 }
++
++/* MC firmware */
++#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
++#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
++#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
++#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
++#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
++
++/* Define phy_reset function to boot the MC based on mcinitcmd.
++ * This happens late enough to properly fixup u-boot env MAC addresses.
++ */
++#define CONFIG_RESET_PHY_R
++
++/*
++ * Carve out a DDR region which will not be used by u-boot/Linux
++ *
++ * It will be used by MC and Debug Server. The MC region must be
++ * 512MB aligned, so the min size to hide is 512MB.
++ */
++#ifdef CONFIG_FSL_MC_ENET
++#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
++#endif
++
++/* USB */
++
++#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
++
++#define HWCONFIG_BUFFER_SIZE 128
++
++/*
++ * Memory Layout Ovverview:
++ *
++ */
++
++/*
++ * Boot-Media Latout:
++ * - SD/eMMC MC offsets (in sectors):
++ * - 0x3000: kernel header
++ * - 0x3200: mc firmware header
++ * - 0x3400: dpc header
++ * - 0x5000: firmware
++ * - 0x6800: dpl
++ * - 0x7000: dpc
++ * - 0x7800: dtb
++ * - 0x8000: kernel
++ * - SPI offsets (in byte):
++ * - 0x0600000: kernel header
++ * - 0x0640000: mc firmware header
++ * - 0x0680000: dpc header
++ * - 0x0a00000: mc firmware
++ * - 0x0e00000: dpc
++ * - 0x0d00000: dpl
++ * - 0x0f00000: dtb
++ * - 0x1000000: kernel
++ */
++
++/*
++ * Load Adresses (different from lx2160a_common.h):
++ * Use GPP DRAM Region #1 (2GB: [0x80000000-0xffffffff]).
++ * - 16MB for secure-boot / mc ([0x80000000-0x80ffffff])
++ * - 1MB for boot-script
++ * - 1MB for pxe
++ * - 1MB for DTB
++ * - 64MB for compressed kernel
++ * - 512MB for uncompressed kernel
++ * - ~1.5GB for ramdisk
++ */
++#define SCRIPT_ADDR_R __stringify(0x81000000)
++#define PXEFILE_ADDR_R __stringify(0x81100000)
++#define FDT_ADDR_R __stringify(0x81200000)
++#define KERNEL_COMP_ADDR_R __stringify(0x81300000)
++#define KERNEL_COMP_SIZE __stringify(0x04000000)
++#define KERNEL_ADDR_R __stringify(0x85300000)
++#define RAMDISK_ADDR_R __stringify(0xa5300000)
++#define FDT_RELOCATION_LIMIT __stringify(0xffffffff)
++
++/* Initial environment variables */
++#define XSPI_MC_INIT_CMD \
++ "sf probe 0:0 && " \
++ "sf read 0x80640000 0x640000 0x80000 && " \
++ "sf read $fdt_addr_r 0xf00000 0x100000 && " \
++ "env exists secureboot && " \
++ "esbc_validate 0x80640000 && " \
++ "esbc_validate 0x80680000; " \
++ "sf read 0x80a00000 0xa00000 0x300000 && " \
++ "sf read 0x80e00000 0xe00000 0x100000; " \
++ "fsl_mc start mc 0x80a00000 0x80e00000\0"
++
++#define SD_MC_INIT_CMD \
++ "mmc read 0x80a00000 0x5000 0x1200;" \
++ "mmc read 0x80e00000 0x7000 0x800;" \
++ "mmc read $fdt_addr_r 0x7800 0x800;" \
++ "env exists secureboot && " \
++ "mmc read 0x80640000 0x3200 0x20 && " \
++ "mmc read 0x80680000 0x3400 0x20 && " \
++ "esbc_validate 0x80640000 && " \
++ "esbc_validate 0x80680000 ;" \
++ "fsl_mc start mc 0x80a00000 0x80e00000\0"
++
++#define SD2_MC_INIT_CMD \
++ "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \
++ "mmc read 0x80e00000 0x7000 0x800;" \
++ "mmc read $fdt_addr_r 0x7800 0x800;" \
++ "env exists secureboot && " \
++ "mmc read 0x80640000 0x3200 0x20 && " \
++ "mmc read 0x80680000 0x3400 0x20 && " \
++ "esbc_validate 0x80640000 && " \
++ "esbc_validate 0x80680000 ;" \
++ "fsl_mc start mc 0x80a00000 0x80e00000\0"
++
++#define EXTRA_ENV_SETTINGS \
++ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
++ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
++ "fdt_high=" FDT_RELOCATION_LIMIT "\0" \
++ "initrd_high=0xffffffffffffffff\0" \
++ "kernel_start=0x1000000\0" \
++ "kernelheader_start=0x600000\0" \
++ "scriptaddr=" SCRIPT_ADDR_R "\0" \
++ "scripthdraddr=0x80080000\0" \
++ "fdtheader_addr_r=0x80100000\0" \
++ "kernelheader_addr_r=0x80200000\0" \
++ "kernel_addr_r=" KERNEL_ADDR_R "\0" \
++ "kernelheader_size=0x40000\0" \
++ "fdt_addr_r=" FDT_ADDR_R "\0" \
++ "fdt_addr=" FDT_ADDR_R "\0" \
++ "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
++ "kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \
++ "kernel_comp_size=" KERNEL_COMP_SIZE "\0" \
++ "load_addr=" KERNEL_ADDR_R "\0" \
++ "kernel_size=0x2800000\0" \
++ "kernel_addr_sd=0x8000\0" \
++ "kernelhdr_addr_sd=0x3000\0" \
++ "kernel_size_sd=0x14000\0" \
++ "kernelhdr_size_sd=0x20\0" \
++ "console=ttyAMA0,115200n8\0" \
++ BOOTENV \
++ "mcmemsize=0x70000000\0" \
++ XSPI_MC_INIT_CMD \
++ "scan_dev_for_boot_part=" \
++ "part list ${devtype} ${devnum} devplist; " \
++ "env exists devplist || setenv devplist 1; " \
++ "for distro_bootpart in ${devplist}; do " \
++ "if fstype ${devtype} " \
++ "${devnum}:${distro_bootpart} " \
++ "bootfstype; then " \
++ "run scan_dev_for_boot; " \
++ "fi; " \
++ "done\0" \
++ "boot_a_script=" \
++ "load ${devtype} ${devnum}:${distro_bootpart} " \
++ "${scriptaddr} ${prefix}${script}; " \
++ "env exists secureboot && load ${devtype} " \
++ "${devnum}:${distro_bootpart} " \
++ "${scripthdraddr} ${prefix}${boot_script_hdr} " \
++ "&& esbc_validate ${scripthdraddr};" \
++ "source ${scriptaddr}\0"
++
++#define XSPI_NOR_BOOTCOMMAND \
++ "sf probe 0:0; " \
++ "sf read 0x806c0000 0x6c0000 0x40000; " \
++ "env exists mcinitcmd && env exists secureboot" \
++ " && esbc_validate 0x806c0000; " \
++ "sf read 0x80d00000 0xd00000 0x100000; " \
++ "env exists mcinitcmd && " \
++ "fsl_mc lazyapply dpl 0x80d00000; " \
++ "run distro_bootcmd;run xspi_bootcmd; " \
++ "env exists secureboot && esbc_halt;"
++
++#define SD_BOOTCOMMAND \
++ "env exists mcinitcmd && mmcinfo; " \
++ "mmc read 0x80d00000 0x6800 0x800; " \
++ "env exists mcinitcmd && env exists secureboot " \
++ " && mmc read 0x806C0000 0x3600 0x20 " \
++ "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
++ "&& fsl_mc lazyapply dpl 0x80d00000;" \
++ "run distro_bootcmd;run sd_bootcmd;" \
++ "env exists secureboot && esbc_halt;"
++
++#define SD2_BOOTCOMMAND \
++ "mmc dev 1; env exists mcinitcmd && mmcinfo; " \
++ "mmc read 0x80d00000 0x6800 0x800; " \
++ "env exists mcinitcmd && env exists secureboot " \
++ " && mmc read 0x806C0000 0x3600 0x20 " \
++ "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
++ "&& fsl_mc lazyapply dpl 0x80d00000;" \
++ "run distro_bootcmd;run sd2_bootcmd;" \
++ "env exists secureboot && esbc_halt;"
++
++/* configure boot order for distro-boot feature */
++#define BOOT_TARGET_DEVICES(func) \
++ func(USB, usb, 0) \
++ func(MMC, mmc, 0) \
++ func(MMC, mmc, 1) \
++ func(NVME, nvme, 0) \
++ func(SCSI, scsi, 0) \
++ func(SCSI, scsi, 1) \
++ func(SCSI, scsi, 2) \
++ func(SCSI, scsi, 3) \
++ func(PXE, pxe, na) \
++ func(DHCP, dhcp, na)
++#include <config_distro_bootcmd.h>
++
++#define CFG_EXTRA_ENV_SETTINGS \
++ EXTRA_ENV_SETTINGS \
++ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
++ "boot_scripts=lx2160acex7_boot.scr\0" \
++ "boot_script_hdr=hdr_lx2160acex7_bs.out\0" \
++ "BOARD=lx2160acex7\0" \
++ "xspi_bootcmd=echo Trying load from flexspi..;" \
++ "sf probe 0:0 && sf read $load_addr " \
++ "$kernel_start $kernel_size ; env exists secureboot &&" \
++ "sf read $kernelheader_addr_r $kernelheader_start " \
++ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
++ " bootm $load_addr#$BOARD\0" \
++ "sd_bootcmd=echo Trying load from sd card..;" \
++ "mmc dev 0; mmcinfo; mmc read $load_addr " \
++ "$kernel_addr_sd $kernel_size_sd ;" \
++ "env exists secureboot && mmc read $kernelheader_addr_r "\
++ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
++ " && esbc_validate ${kernelheader_addr_r};" \
++ "bootm $load_addr#$BOARD\0" \
++ "sd2_bootcmd=echo Trying load from emmc card..;" \
++ "mmc dev 1; mmcinfo; mmc read $load_addr " \
++ "$kernel_addr_sd $kernel_size_sd ;" \
++ "env exists secureboot && mmc read $kernelheader_addr_r "\
++ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
++ " && esbc_validate ${kernelheader_addr_r};" \
++ "bootm $load_addr#$BOARD\0"
++
++#include <asm/fsl_secure_boot.h>
++
++#endif /* __CONFIG_LX2160ACEX7_H */
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0012-board-solidrun-lx2160cex7-add-support-for-lx2162-som.patch b/board/solidrun/lx2160acex7/patches/uboot/0012-board-solidrun-lx2160cex7-add-support-for-lx2162-som.patch
new file mode 100644
index 0000000000..ad22325429
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0012-board-solidrun-lx2160cex7-add-support-for-lx2162-som.patch
@@ -0,0 +1,164 @@
+From 3c3574b43142bba7a47da360b8bbc599f17a2f71 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Fri, 8 Aug 2025 14:17:13 +0200
+Subject: [PATCH 12/14] board: solidrun: lx2160cex7: add support for lx2162 som
+
+Compile with CONFIG_DEFAULT_DEVICE_TREE=fsl-lx2162a-sr-som
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ arch/arm/dts/fsl-lx2162a-sr-som-u-boot.dtsi | 19 +++++
+ arch/arm/dts/fsl-lx2162a-sr-som.dts | 25 +++++++
+ arch/arm/dts/fsl-lx2162a-sr-som.dtsi | 82 +++++++++++++++++++++
+ 3 files changed, 126 insertions(+)
+ create mode 100644 arch/arm/dts/fsl-lx2162a-sr-som-u-boot.dtsi
+ create mode 100644 arch/arm/dts/fsl-lx2162a-sr-som.dts
+ create mode 100644 arch/arm/dts/fsl-lx2162a-sr-som.dtsi
+
+diff --git a/arch/arm/dts/fsl-lx2162a-sr-som-u-boot.dtsi b/arch/arm/dts/fsl-lx2162a-sr-som-u-boot.dtsi
+new file mode 100644
+index 00000000000..9e29851bb47
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2162a-sr-som-u-boot.dtsi
+@@ -0,0 +1,19 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++ aliases {
++ tlv0 = &config_eeprom;
++ serial0 = &uart0;
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&usb1 {
++ /* u-boot lx2160a.dtsi enabled this by default, but LX2162 has single USB only */
++ status = "disabled";
++};
+diff --git a/arch/arm/dts/fsl-lx2162a-sr-som.dts b/arch/arm/dts/fsl-lx2162a-sr-som.dts
+new file mode 100644
+index 00000000000..21844e9418c
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2162a-sr-som.dts
+@@ -0,0 +1,25 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/*
++ * Device Tree file for LX2162A-SoM Standalone (Generic Carrier Board)
++ *
++ * Copyright 2025 Josua Mayer <josua at solid-run.com>
++ */
++
++/dts-v1/;
++
++#include "fsl-lx2160a.dtsi"
++#include "fsl-lx2162a-sr-som.dtsi"
++
++/ {
++ model = "SolidRun LX2162A System on Module";
++ compatible = "solidrun,lx2162a-som", "fsl,lx2160a";
++};
++
++/* for SD-Card Boot */
++&esdhc0 {
++ sd-uhs-sdr104;
++ sd-uhs-sdr50;
++ sd-uhs-sdr25;
++ sd-uhs-sdr12;
++ status = "okay";
++};
+diff --git a/arch/arm/dts/fsl-lx2162a-sr-som.dtsi b/arch/arm/dts/fsl-lx2162a-sr-som.dtsi
+new file mode 100644
+index 00000000000..e914291e63a
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2162a-sr-som.dtsi
+@@ -0,0 +1,82 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Device Tree file for LX2162A-SOM
++//
++// Copyright 2021 Rabeeh Khoury <rabeeh at solid-run.com>
++// Copyright 2023 Josua Mayer <josua at solid-run.com>
++
++&crypto {
++ status = "okay";
++};
++
++&dpmac17 {
++ phy-handle = <ðernet_phy0>;
++ phy-connection-type = "rgmii-id";
++};
++
++&emdio1 {
++ status = "okay";
++
++ ethernet_phy0: ethernet-phy at 1 {
++ reg = <1>;
++ };
++};
++
++&esdhc1 {
++ bus-width = <8>;
++ mmc-hs200-1_8v;
++ mmc-hs400-1_8v;
++ status = "okay";
++};
++
++&fspi {
++ status = "okay";
++
++ flash at 0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ m25p,fast-read;
++ spi-max-frequency = <50000000>;
++ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
++ spi-rx-bus-width = <8>;
++ spi-tx-bus-width = <1>;
++ };
++};
++
++&i2c0 {
++ status = "okay";
++
++ fan-controller at 18 {
++ compatible = "ti,amc6821";
++ reg = <0x18>;
++ };
++
++ ddr_spd: eeprom at 51 {
++ compatible = "st,24c02", "atmel,24c02";
++ reg = <0x51>;
++ read-only;
++ };
++
++ config_eeprom: eeprom at 57 {
++ compatible = "st,24c02", "atmel,24c02";
++ reg = <0x57>;
++ };
++};
++
++&i2c4 {
++ status = "okay";
++
++ variable_eeprom: eeprom at 54 {
++ compatible = "st,24c2048", "atmel,24c2048";
++ reg = <0x54>;
++ };
++};
++
++&i2c5 {
++ status = "okay";
++
++ rtc at 6f {
++ compatible = "microchip,mcp7940x";
++ reg = <0x6f>;
++ };
++};
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0013-board-solidrun-lx2160cex7-add-support-for-lx2162-cle.patch b/board/solidrun/lx2160acex7/patches/uboot/0013-board-solidrun-lx2160cex7-add-support-for-lx2162-cle.patch
new file mode 100644
index 0000000000..eeac036f93
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0013-board-solidrun-lx2160cex7-add-support-for-lx2162-cle.patch
@@ -0,0 +1,442 @@
+From 9365f95c4a356741ed4706697e33e2244afa5bc6 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Fri, 8 Aug 2025 15:05:58 +0200
+Subject: [PATCH 13/14] board: solidrun: lx2160cex7: add support for lx2162
+ clearfog
+
+Compile with CONFIG_DEFAULT_DEVICE_TREE=fsl-lx2162a-clearfog
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ arch/arm/dts/fsl-lx2162a-clearfog-u-boot.dtsi | 43 +++
+ arch/arm/dts/fsl-lx2162a-clearfog.dts | 355 ++++++++++++++++++
+ configs/lx2160acex7_tfa_defconfig | 1 +
+ 3 files changed, 399 insertions(+)
+ create mode 100644 arch/arm/dts/fsl-lx2162a-clearfog-u-boot.dtsi
+ create mode 100644 arch/arm/dts/fsl-lx2162a-clearfog.dts
+
+diff --git a/arch/arm/dts/fsl-lx2162a-clearfog-u-boot.dtsi b/arch/arm/dts/fsl-lx2162a-clearfog-u-boot.dtsi
+new file mode 100644
+index 00000000000..b253888e620
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2162a-clearfog-u-boot.dtsi
+@@ -0,0 +1,43 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include "fsl-lx2162a-sr-som-u-boot.dtsi"
++
++&dpmac11 {
++ /* link pcs phy as second phy for sgmii mac link-type phy */
++ phy-handle = <ðernet_phy3>, <&pcs11>;
++};
++
++&dpmac12 {
++ /* link pcs phy as second phy for sgmii mac link-type phy */
++ phy-handle = <ðernet_phy1>, <&pcs12>;
++};
++
++&dpmac13 {
++ /* link pcs phy as second phy for sgmii mac link-type phy */
++ phy-handle = <ðernet_phy6>, <&pcs13>;
++};
++
++&dpmac14 {
++ /* link pcs phy as second phy for sgmii mac link-type phy */
++ phy-handle = <ðernet_phy8>, <&pcs14>;
++};
++
++&dpmac15 {
++ /* link pcs phy as second phy for sgmii mac link-type phy */
++ phy-handle = <ðernet_phy4>, <&pcs15>;
++};
++
++&dpmac16 {
++ /* link pcs phy as second phy for sgmii mac link-type phy */
++ phy-handle = <ðernet_phy2>, <&pcs16>;
++};
++
++&dpmac17 {
++ /* link pcs phy as second phy for sgmii mac link-type phy */
++ phy-handle = <ðernet_phy0>, <&pcs17>;
++};
++
++&dpmac18 {
++ /* link pcs phy as second phy for sgmii mac link-type phy */
++ phy-handle = <ðernet_phy7>, <&pcs18>;
++};
+diff --git a/arch/arm/dts/fsl-lx2162a-clearfog.dts b/arch/arm/dts/fsl-lx2162a-clearfog.dts
+new file mode 100644
+index 00000000000..be26890a11c
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2162a-clearfog.dts
+@@ -0,0 +1,355 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Device Tree file for LX2162A Clearfog
++//
++// Copyright 2023 Josua Mayer <josua at solid-run.com>
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++
++#include "fsl-lx2160a.dtsi"
++#include "fsl-lx2162a-sr-som.dtsi"
++
++/ {
++ model = "SolidRun LX2162A Clearfog";
++ compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";
++
++ aliases {
++ crypto = &crypto;
++ i2c0 = &i2c0;
++ i2c1 = &i2c2;
++ i2c2 = &i2c4;
++ i2c3 = &sfp_i2c0;
++ i2c4 = &sfp_i2c1;
++ i2c5 = &sfp_i2c2;
++ i2c6 = &sfp_i2c3;
++ i2c7 = &mpcie1_i2c;
++ i2c8 = &mpcie0_i2c;
++ i2c9 = &pcieclk_i2c;
++ i2c10 = &i2c5;
++ mmc0 = &esdhc0;
++ mmc1 = &esdhc1;
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ led_sfp_at: led-sfp-at {
++ gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
++ default-state = "off";
++ };
++
++ led_sfp_ab: led-sfp-ab {
++ gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
++ default-state = "off";
++ };
++
++ led_sfp_bt: led-sfp-bt {
++ gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
++ default-state = "off";
++ };
++
++ led_sfp_bb: led-sfp-bb {
++ gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
++ default-state = "off";
++ };
++ };
++
++ sfp_at: sfp-at {
++ compatible = "sff,sfp";
++ i2c-bus = <&sfp_i2c0>;
++ mod-def0-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */
++ maximum-power-milliwatt = <2000>;
++ };
++
++ sfp_ab: sfp-ab {
++ compatible = "sff,sfp";
++ i2c-bus = <&sfp_i2c1>;
++ mod-def0-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */
++ maximum-power-milliwatt = <2000>;
++ };
++
++ sfp_bt: sfp-bt {
++ compatible = "sff,sfp";
++ i2c-bus = <&sfp_i2c2>;
++ mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */
++ maximum-power-milliwatt = <2000>;
++ };
++
++ sfp_bb: sfp-bb {
++ compatible = "sff,sfp";
++ i2c-bus = <&sfp_i2c3>;
++ mod-def0-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */
++ maximum-power-milliwatt = <2000>;
++ };
++};
++
++&dpmac3 {
++ sfp = <&sfp_at>;
++ managed = "in-band-status";
++};
++
++&dpmac4 {
++ sfp = <&sfp_ab>;
++ managed = "in-band-status";
++};
++
++&dpmac5 {
++ sfp = <&sfp_bt>;
++ managed = "in-band-status";
++};
++
++&dpmac6 {
++ sfp = <&sfp_bb>;
++ managed = "in-band-status";
++};
++
++&dpmac11 {
++ phy-handle = <ðernet_phy3>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac12 {
++ phy-handle = <ðernet_phy1>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac13 {
++ phy-handle = <ðernet_phy6>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac14 {
++ phy-handle = <ðernet_phy8>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac15 {
++ phy-handle = <ðernet_phy4>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac16 {
++ phy-handle = <ðernet_phy2>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac17 {
++ /* override connection to on-SoM phy */
++ /delete-property/ phy-handle;
++ /delete-property/ phy-connection-type;
++
++ phy-handle = <ðernet_phy5>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&dpmac18 {
++ phy-handle = <ðernet_phy7>, <&pcs18>;
++ phy-connection-type = "sgmii";
++ status = "okay";
++};
++
++&emdio1 {
++ ethernet_phy1: ethernet-phy at 8 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <8>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy2: ethernet-phy at 9 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <9>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy3: ethernet-phy at 10 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <10>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy4: ethernet-phy at 11 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <11>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy5: ethernet-phy at 12 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <12>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy6: ethernet-phy at 13 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <13>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy7: ethernet-phy at 14 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <14>;
++ max-speed = <1000>;
++ };
++
++ ethernet_phy8: ethernet-phy at 15 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <15>;
++ max-speed = <1000>;
++ };
++};
++
++&esdhc0 {
++ sd-uhs-sdr104;
++ sd-uhs-sdr50;
++ sd-uhs-sdr25;
++ sd-uhs-sdr12;
++ status = "okay";
++};
++
++ðernet_phy0 {
++ /*
++ * SoM has a phy at address 1 connected to SoC Ethernet Controller 1.
++ * It competes for WRIOP MAC17, and no connector has been wired.
++ */
++ status = "disabled";
++};
++
++&i2c2 {
++ status = "okay";
++
++ /* retimer at 18 */
++
++ i2c-mux at 70 {
++ compatible = "nxp,pca9546";
++ reg = <0x70>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ i2c-mux-idle-disconnect;
++
++ sfp_i2c0: i2c at 0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++ };
++
++ sfp_i2c1: i2c at 1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++ };
++
++ sfp_i2c2: i2c at 2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++ };
++
++ sfp_i2c3: i2c at 3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++ };
++ };
++
++ i2c-mux at 71 {
++ compatible = "nxp,pca9546";
++ reg = <0x71>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ i2c-mux-idle-disconnect;
++
++ mpcie1_i2c: i2c at 0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++ };
++
++ mpcie0_i2c: i2c at 1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++ };
++
++ pcieclk_i2c: i2c at 2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++
++ /* clock-controller at 6b */
++ };
++ };
++};
++
++&pcie3 {
++ status = "disabled";
++};
++
++&pcie4 {
++ status = "disabled";
++};
++
++&pcs_mdio3 {
++ status = "okay";
++};
++
++&pcs_mdio4 {
++ status = "okay";
++};
++
++&pcs_mdio5 {
++ status = "okay";
++};
++
++&pcs_mdio6 {
++ status = "okay";
++};
++
++&pcs_mdio11 {
++ status = "okay";
++};
++
++&pcs_mdio12 {
++ status = "okay";
++};
++
++&pcs_mdio13 {
++ status = "okay";
++};
++
++&pcs_mdio14 {
++ status = "okay";
++};
++
++&pcs_mdio15 {
++ status = "okay";
++};
++
++&pcs_mdio16 {
++ status = "okay";
++};
++
++&pcs_mdio17 {
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&usb0 {
++ status = "okay";
++};
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 016daa899c8..9b8a99f868b 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -82,6 +82,7 @@ CONFIG_SPI_FLASH_WINBOND=y
+ CONFIG_PHYLIB=y
+ CONFIG_PHY_AQUANTIA=y
+ CONFIG_PHY_ATHEROS=y
++CONFIG_PHY_MARVELL_10G=y
+ CONFIG_FSL_MEMAC=y
+ CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
+ CONFIG_DM_ETH_PHY=y
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0014-board-solidrun-lx2160cex7-add-support-for-clearfog-c.patch b/board/solidrun/lx2160acex7/patches/uboot/0014-board-solidrun-lx2160cex7-add-support-for-clearfog-c.patch
new file mode 100644
index 0000000000..fbc2a5f7c7
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0014-board-solidrun-lx2160cex7-add-support-for-clearfog-c.patch
@@ -0,0 +1,238 @@
+From c932c5e0139c026c82bb0bdf7e27117d8a13590c Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Fri, 8 Aug 2025 18:05:24 +0200
+Subject: [PATCH 14/14] board: solidrun: lx2160cex7: add support for
+ clearfog-cx & honeycomb
+
+Compile with CONFIG_DEFAULT_DEVICE_TREE=fsl-lx2160a-clearfog-cx
+or CONFIG_DEFAULT_DEVICE_TREE=fsl-lx2160a-honeycomb
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ .../dts/fsl-lx2160a-clearfog-cx-u-boot.dtsi | 3 +
+ arch/arm/dts/fsl-lx2160a-clearfog-cx.dts | 15 ++
+ .../dts/fsl-lx2160a-clearfog-itx-u-boot.dtsi | 3 +
+ arch/arm/dts/fsl-lx2160a-clearfog-itx.dtsi | 135 ++++++++++++++++++
+ .../arm/dts/fsl-lx2160a-honeycomb-u-boot.dtsi | 3 +
+ arch/arm/dts/fsl-lx2160a-honeycomb.dts | 15 ++
+ 6 files changed, 174 insertions(+)
+ create mode 100644 arch/arm/dts/fsl-lx2160a-clearfog-cx-u-boot.dtsi
+ create mode 100644 arch/arm/dts/fsl-lx2160a-clearfog-cx.dts
+ create mode 100644 arch/arm/dts/fsl-lx2160a-clearfog-itx-u-boot.dtsi
+ create mode 100644 arch/arm/dts/fsl-lx2160a-clearfog-itx.dtsi
+ create mode 100644 arch/arm/dts/fsl-lx2160a-honeycomb-u-boot.dtsi
+ create mode 100644 arch/arm/dts/fsl-lx2160a-honeycomb.dts
+
+diff --git a/arch/arm/dts/fsl-lx2160a-clearfog-cx-u-boot.dtsi b/arch/arm/dts/fsl-lx2160a-clearfog-cx-u-boot.dtsi
+new file mode 100644
+index 00000000000..fc1b1692755
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-clearfog-cx-u-boot.dtsi
+@@ -0,0 +1,3 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include "fsl-lx2160a-clearfog-itx-u-boot.dtsi"
+diff --git a/arch/arm/dts/fsl-lx2160a-clearfog-cx.dts b/arch/arm/dts/fsl-lx2160a-clearfog-cx.dts
+new file mode 100644
+index 00000000000..86a9b771428
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-clearfog-cx.dts
+@@ -0,0 +1,15 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Device Tree file for LX2160A Clearfog CX board
++//
++// Copyright 2019 SolidRun Ltd.
++
++/dts-v1/;
++
++#include "fsl-lx2160a-clearfog-itx.dtsi"
++
++/ {
++ model = "SolidRun LX2160A Clearfog CX";
++ compatible = "solidrun,clearfog-cx",
++ "solidrun,lx2160a-cex7", "fsl,lx2160a";
++};
+diff --git a/arch/arm/dts/fsl-lx2160a-clearfog-itx-u-boot.dtsi b/arch/arm/dts/fsl-lx2160a-clearfog-itx-u-boot.dtsi
+new file mode 100644
+index 00000000000..2ab1b63addf
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-clearfog-itx-u-boot.dtsi
+@@ -0,0 +1,3 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include "fsl-lx2160a-cex7-u-boot.dtsi"
+diff --git a/arch/arm/dts/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm/dts/fsl-lx2160a-clearfog-itx.dtsi
+new file mode 100644
+index 00000000000..91a2fd0c260
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-clearfog-itx.dtsi
+@@ -0,0 +1,135 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Device Tree file for LX2160A Clearfog ITX board; this contains the
++// common parts shared between the Clearfog CX and Honeycomb builds.
++//
++// Copyright 2019 SolidRun Ltd.
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++
++#include "fsl-lx2160a-cex7.dtsi"
++#include <dt-bindings/input/linux-event-codes.h>
++
++/ {
++ aliases {
++ serial0 = &uart0;
++ serial1 = &uart1;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++
++ key {
++ label = "power";
++ linux,can-disable;
++ linux,code = <KEY_POWER>;
++ gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ sfp0: sfp-0 {
++ compatible = "sff,sfp";
++ i2c-bus = <&sfp0_i2c>;
++ mod-def0-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ sfp1: sfp-1 {
++ compatible = "sff,sfp";
++ i2c-bus = <&sfp1_i2c>;
++ mod-def0-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ sfp2: sfp-2 {
++ compatible = "sff,sfp";
++ i2c-bus = <&sfp2_i2c>;
++ mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ sfp3: sfp-3 {
++ compatible = "sff,sfp";
++ i2c-bus = <&sfp3_i2c>;
++ mod-def0-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++};
++
++&dpmac7 {
++ sfp = <&sfp0>;
++ managed = "in-band-status";
++};
++
++&dpmac8 {
++ sfp = <&sfp1>;
++ managed = "in-band-status";
++};
++
++&dpmac9 {
++ sfp = <&sfp2>;
++ managed = "in-band-status";
++};
++
++&dpmac10 {
++ sfp = <&sfp3>;
++ managed = "in-band-status";
++};
++
++&emdio2 {
++ status = "okay";
++};
++
++&esdhc0 {
++ sd-uhs-sdr104;
++ sd-uhs-sdr50;
++ sd-uhs-sdr25;
++ sd-uhs-sdr12;
++ status = "okay";
++};
++
++&pcs_mdio7 {
++ status = "okay";
++};
++
++&pcs_mdio8 {
++ status = "okay";
++};
++
++&pcs_mdio9 {
++ status = "okay";
++};
++
++&pcs_mdio10 {
++ status = "okay";
++};
++
++&sata0 {
++ status = "okay";
++};
++
++&sata1 {
++ status = "okay";
++};
++
++&sata2 {
++ status = "okay";
++};
++
++&sata3 {
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&uart1 {
++ status = "okay";
++};
+diff --git a/arch/arm/dts/fsl-lx2160a-honeycomb-u-boot.dtsi b/arch/arm/dts/fsl-lx2160a-honeycomb-u-boot.dtsi
+new file mode 100644
+index 00000000000..fc1b1692755
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-honeycomb-u-boot.dtsi
+@@ -0,0 +1,3 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include "fsl-lx2160a-clearfog-itx-u-boot.dtsi"
+diff --git a/arch/arm/dts/fsl-lx2160a-honeycomb.dts b/arch/arm/dts/fsl-lx2160a-honeycomb.dts
+new file mode 100644
+index 00000000000..fe19f3009ea
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-honeycomb.dts
+@@ -0,0 +1,15 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Device Tree file for LX2160A Honeycomb board
++//
++// Copyright 2019 SolidRun Ltd.
++
++/dts-v1/;
++
++#include "fsl-lx2160a-clearfog-itx.dtsi"
++
++/ {
++ model = "SolidRun LX2160A Honeycomb";
++ compatible = "solidrun,honeycomb",
++ "solidrun,lx2160a-cex7", "fsl,lx2160a";
++};
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0015-board-solidrun-lx2160cex7-configure-fan-controller-d.patch b/board/solidrun/lx2160acex7/patches/uboot/0015-board-solidrun-lx2160cex7-configure-fan-controller-d.patch
new file mode 100644
index 0000000000..ec84d99033
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0015-board-solidrun-lx2160cex7-configure-fan-controller-d.patch
@@ -0,0 +1,138 @@
+From 5a25d2b4237e08345c61c8e9affa34031c2363ac Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sat, 9 Aug 2025 15:25:05 +0200
+Subject: [PATCH] board: solidrun: lx2160cex7: configure fan-controller
+ defaults
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Configure default values for fan-controller register according to
+maximum ratings of LX2160/LX2162 SoC tuned for quiet operation.
+
+Fan starts to speed up at 64°C, reaching maximum at 101°C - 4° short of
+SoC absolute maximum. LX2160 is designed to support continuous operation
+at 105°C junction.
+
+Linux driver keeps bootloader defaults till the user applies changes
+through sysfs interface.
+
+After communication with fan-controller succeeded, release the gpio
+forcing full-speed to allow quiet operation.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi | 22 ---------
+ board/solidrun/lx2160acex7/lx2160a.c | 55 ++++++++++++++++++++++-
+ 2 files changed, 54 insertions(+), 23 deletions(-)
+
+diff --git a/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi b/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi
+index 9394c36d70e..0e547229d74 100644
+--- a/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi
++++ b/arch/arm/dts/fsl-lx2160a-cex7-u-boot.dtsi
+@@ -9,28 +9,6 @@
+ };
+ };
+
+-&gpio2 {
+- /*
+- * AMC6821 THERM signal uses open-drain logic and can be driven
+- * by either the host (force full-speed) or the chip
+- * (thermal warning). Firmware drives it low during reset.
+- *
+- * Force fan full-speed while bootloader is active.
+- * TODO: Add fan-controller driver.
+- */
+- fan-full-speed-hog {
+- gpio-hog;
+- gpios = <2 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+- output-high;
+- line-name = "fan-full-speed";
+- };
+-};
+-
+-&{/i2c at 2000000/i2c-mux at 77/i2c at 1/fan-temperature-ctrlr at 18} {
+- /*u-boot does not currently have a driver for this fan-controller */
+- status = "disabled";
+-};
+-
+ &uart0 {
+ status = "okay";
+ };
+diff --git a/board/solidrun/lx2160acex7/lx2160a.c b/board/solidrun/lx2160acex7/lx2160a.c
+index 632fbff52dc..f6b3856b8dc 100644
+--- a/board/solidrun/lx2160acex7/lx2160a.c
++++ b/board/solidrun/lx2160acex7/lx2160a.c
+@@ -18,6 +18,7 @@
+ #include <fsl_ddr.h>
+ #include <init.h>
+ #include <malloc.h>
++#include <i2c.h>
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+@@ -151,8 +152,60 @@ int board_init(void)
+ }
+
+ #ifdef CONFIG_BOARD_LATE_INIT
++static int setup_fan_ctrl(void) {
++ int ret = -ENODEV;
++ struct udevice *bus, *dev;
++
++ struct {
++ const char *const machine;
++ const char *const bus;
++ uint8_t addr;
++ u32 __iomem *const gpio_reg;
++ uint32_t gpio_mask;
++ } fanctrl[] = {
++ {
++ .machine = "solidrun,lx2160a-cex7",
++ .bus = "i2c at 2000000->i2c-mux at 77->i2c at 1",
++ .addr = 0x18,
++ .gpio_reg = (void *)0x02320000,
++ .gpio_mask = (1 << 29),
++ }, {
++ .machine = "solidrun,lx2162a-som",
++ .bus = "i2c at 2000000",
++ .addr = 0x18,
++ },
++ };
++
++ for (int i = 0; i < ARRAY_SIZE(fanctrl); i++) {
++ if (!of_machine_is_compatible(fanctrl[i].machine))
++ continue;
++
++ ret = uclass_get_device_by_name(UCLASS_I2C, fanctrl[i].bus, &bus);
++ if (ret)
++ continue;
++
++ ret = i2c_get_chip(bus, fanctrl[i].addr, 1, &dev);
++ if (ret)
++ continue;
++
++ /* set low temperatur threshold 64C, slope 1.57%/C, full-speed at 101C (safe for LX2160/LX2162 SoC) */
++ ret = dm_i2c_reg_write(dev, 0x25, 0x83);
++ if (ret)
++ continue;
++
++ /* change gpio direction from output to input for low->high transition with external PU */
++ if (fanctrl[i].gpio_reg)
++ *fanctrl[i].gpio_reg &= ~fanctrl[i].gpio_mask;
++
++ printf("Fan: Low 64°C, High 101°C, Slope 1.57%\n");
++ }
++
++ return ret;
++}
++
+ int fsl_board_late_init(void) {
+- /* TODO: configure fan-controller here and release gpio-hog */
++ setup_fan_ctrl();
++
+ return 0;
+ }
+ #endif
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0016-board-solidrun-lx2160cex7-fix-read-rcw-from-dcsr-mem.patch b/board/solidrun/lx2160acex7/patches/uboot/0016-board-solidrun-lx2160cex7-fix-read-rcw-from-dcsr-mem.patch
new file mode 100644
index 0000000000..122645e8fe
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0016-board-solidrun-lx2160cex7-fix-read-rcw-from-dcsr-mem.patch
@@ -0,0 +1,48 @@
+From 86632dc5b14530a088c87e0513caae4784d5cd43 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sat, 9 Aug 2025 18:54:35 +0200
+Subject: [PATCH 16/17] board: solidrun: lx2160cex7: fix read rcw from dcsr
+ memory
+
+LX2160 can override RCW configuration at runtime in the DCSR memory at
+0x700100100 and following while the original values in the DCFG memory
+at 0x01e00100 are read-only.
+
+The DCSR area however must be initialised by a write before
+reading from it, otherwise zero is read.
+
+This causes several subtle bugs, e.g. introduced by mainline kernel
+since 6.12 changing pinmux of i2c does accidentally also change sdhc
+card-detect pinmux causing software to detect sdcard removal during
+boot.
+
+Copy the RCW from DCFG to DCSR during board_early_init_f to ensure
+successive reads from the reconfiguration area are valid.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ board/solidrun/lx2160acex7/lx2160a.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/board/solidrun/lx2160acex7/lx2160a.c b/board/solidrun/lx2160acex7/lx2160a.c
+index f6b3856b8dc..76302e8e568 100644
+--- a/board/solidrun/lx2160acex7/lx2160a.c
++++ b/board/solidrun/lx2160acex7/lx2160a.c
+@@ -25,6 +25,14 @@ DECLARE_GLOBAL_DATA_PTR;
+ int board_early_init_f(void)
+ {
+ fsl_lsch3_early_init_f();
++
++ /*
++ * RCW DCSR area for runtime re-configuration must be written
++ * before read to avoid reading (invalid) zeros.
++ * copy RCW values from read-only DCFG to read-write DCSR.
++ */
++ memcpy((void *)0x700100100, (void *)0x01e00100, 0x180);
++
+ return 0;
+ }
+
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0017-board-solidrun-lx2160cex7-add-support-for-half-twins.patch b/board/solidrun/lx2160acex7/patches/uboot/0017-board-solidrun-lx2160cex7-add-support-for-half-twins.patch
new file mode 100644
index 0000000000..2e33194f8c
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0017-board-solidrun-lx2160cex7-add-support-for-half-twins.patch
@@ -0,0 +1,634 @@
+From 541a04ad7e7e147b51db8d6cad1fcfcc73be04e1 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sat, 9 Aug 2025 16:28:08 +0200
+Subject: [PATCH] board: solidrun: lx2160cex7: add support for half-twins board
+
+Compile with CONFIG_DEFAULT_DEVICE_TREE=fsl-lx2160a-half-twins
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ .../dts/fsl-lx2160a-half-twins-u-boot.dtsi | 7 +
+ arch/arm/dts/fsl-lx2160a-half-twins.dts | 584 ++++++++++++++++++
+ configs/lx2160acex7_tfa_defconfig | 1 +
+ 3 files changed, 592 insertions(+)
+ create mode 100644 arch/arm/dts/fsl-lx2160a-half-twins-u-boot.dtsi
+ create mode 100644 arch/arm/dts/fsl-lx2160a-half-twins.dts
+
+diff --git a/arch/arm/dts/fsl-lx2160a-half-twins-u-boot.dtsi b/arch/arm/dts/fsl-lx2160a-half-twins-u-boot.dtsi
+new file mode 100644
+index 00000000000..25031b98a7a
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-half-twins-u-boot.dtsi
+@@ -0,0 +1,7 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include "fsl-lx2160a-cex7-u-boot.dtsi"
++
++&usb1 {
++ status = "disabled";
++};
+diff --git a/arch/arm/dts/fsl-lx2160a-half-twins.dts b/arch/arm/dts/fsl-lx2160a-half-twins.dts
+new file mode 100644
+index 00000000000..497d56036e2
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-half-twins.dts
+@@ -0,0 +1,584 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Device Tree file for LX2160A based half twins
++//
++// Copyright 2022 SolidRun Ltd.
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++
++#include "fsl-lx2160a-cex7.dtsi"
++
++/ {
++ model = "SolidRun LX2160A Twins";
++ compatible = "solidrun,clearfog-twins",
++ "solidrun,lx2160a-cex7", "fsl,lx2160a";
++
++ aliases {
++ i2c0 = &i2c0;
++ i2c1 = &i2c2;
++ i2c2 = &i2c4;
++ i2c3 = &{/i2c at 2000000/i2c-mux at 77/i2c at 1};
++ i2c4 = &{/i2c at 2000000/i2c-mux at 77/i2c at 2};
++ i2c5 = &{/i2c at 2000000/i2c-mux at 77/i2c at 3};
++ i2c6 = &sfp0_i2c;
++ i2c7 = &sfp1_i2c;
++ i2c8 = &sfp2_i2c;
++ i2c9 = &sfp3_i2c;
++ i2c10 = &twins_sfp_c1_at_i2c;
++ i2c11 = &twins_sfp_c1_ab_i2c;
++ i2c12 = &twins_sfp_c1_bt_i2c;
++ i2c13 = &twins_sfp_c1_bb_i2c;
++ i2c14 = &twins_sfp_c2_at_i2c;
++ i2c15 = &twins_sfp_c2_ab_i2c;
++ i2c16 = &twins_sfp_c2_bt_i2c;
++ i2c17 = &twins_sfp_c2_bb_i2c;
++ i2c18 = &twins_sfp_c3_at_i2c;
++ i2c19 = &twins_sfp_c3_ab_i2c;
++ i2c20 = &twins_sfp_c3_bt_i2c;
++ i2c21 = &twins_sfp_c3_bb_i2c;
++ i2c22 = &htwins_sfp_c3_at_i2c;
++ i2c23 = &htwins_sfp_c3_ab_i2c;
++ i2c24 = &htwins_sfp_c3_bt_i2c;
++ i2c25 = &htwins_sfp_c3_bb_i2c;
++ i2c26 = &{/i2c at 2000000/i2c-mux at 77/i2c at 0};
++ mmc0 = &esdhc0;
++ mmc1 = &esdhc1;
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ c1_at_sfp: c1-at-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&twins_sfp_c1_at_i2c>;
++ mod-def0-gpio = <&expander0 1 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ c1_ab_sfp: c1-ab-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&twins_sfp_c1_ab_i2c>;
++ mod-def0-gpio = <&expander0 2 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ c1_bt_sfp: c1-bt-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&twins_sfp_c1_bt_i2c>;
++ mod-def0-gpio = <&expander0 3 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ c1_bb_sfp: c1-bb-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&twins_sfp_c1_bb_i2c>;
++ mod-def0-gpio = <&expander0 4 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ c2_at_sfp: c2-at-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&twins_sfp_c2_at_i2c>;
++ mod-def0-gpio = <&expander0 5 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ c2_ab_sfp: c2-ab-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&twins_sfp_c2_ab_i2c>;
++ mod-def0-gpio = <&expander0 6 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ c2_bt_sfp: c2-bt-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&twins_sfp_c2_bt_i2c>;
++ mod-def0-gpio = <&expander0 9 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ c2_bb_sfp: c2-bb-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&twins_sfp_c2_bb_i2c>;
++ mod-def0-gpio = <&expander0 10 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ c3_at_sfp: c3-at-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&twins_sfp_c3_at_i2c>;
++ mod-def0-gpio = <&expander0 11 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ c3_ab_sfp: c3-ab-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&twins_sfp_c3_ab_i2c>;
++ mod-def0-gpio = <&expander0 12 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ c3_bt_sfp: c3-bt-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&twins_sfp_c3_bt_i2c>;
++ mod-def0-gpio = <&expander0 13 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ c3_bb_sfp: c3-bb-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&twins_sfp_c3_bb_i2c>;
++ mod-def0-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ ht_c3_at_sfp: ht-c3-at-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&htwins_sfp_c3_at_i2c>;
++ mod-def0-gpio = <&expander2 11 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ ht_c3_ab_sfp: ht-c3-ab-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&htwins_sfp_c3_ab_i2c>;
++ mod-def0-gpio = <&expander2 12 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ ht_c3_bt_sfp: ht-c3-bt-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&htwins_sfp_c3_bt_i2c>;
++ mod-def0-gpio = <&expander2 13 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ ht_c3_bb_sfp: ht-c3-bb-sfp {
++ compatible = "sff,sfp";
++ i2c-bus = <&htwins_sfp_c3_bb_i2c>;
++ mod-def0-gpio = <&expander2 14 GPIO_ACTIVE_LOW>;
++ maximum-power-milliwatt = <2000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ led_c1_at: led-c1-at {
++ gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_c1_ab: led-c1-ab {
++ gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_c1_bt: led-c1-bt {
++ gpios = <&expander1 4 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_c1_bb: led-c1-bb {
++ gpios = <&expander1 3 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_c2_at: led-c2-at {
++ gpios = <&expander1 5 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_c2_ab: led-c2-ab {
++ gpios = <&expander1 6 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_c2_bt: led-c2-bt {
++ gpios = <&expander1 10 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_c2_bb: led-c2-bb {
++ gpios = <&expander1 9 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_c3_at: led-c3-at {
++ gpios = <&expander1 11 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_c3_ab: led-c3-ab {
++ gpios = <&expander1 12 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_c3_bt: led-c3-bt {
++ gpios = <&expander1 14 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_c3_bb: led-c3-bb {
++ gpios = <&expander1 13 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_ht_c3_at: led-ht-c3-at {
++ gpios = <&expander3 11 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_ht_c3_ab: led-ht-c3-ab {
++ gpios = <&expander3 12 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_ht_c3_bt: led-ht-c3-bt {
++ gpios = <&expander3 14 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led_ht_c3_bb: led-ht-c3-bb {
++ gpios = <&expander3 13 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ };
++};
++
++&i2c2 {
++ i2c-switch at 76 {
++ compatible = "nxp,pca9547";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x76>;
++ i2c-mux-idle-disconnect;
++
++ twins_sfp_c1_at_i2c: i2c at 1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++ };
++
++ twins_sfp_c1_ab_i2c: i2c at 2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++ };
++
++ twins_sfp_c1_bt_i2c: i2c at 3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++ };
++
++ twins_sfp_c1_bb_i2c: i2c at 4 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <4>;
++ };
++
++ twins_sfp_c2_at_i2c: i2c at 5 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <5>;
++ };
++
++ twins_sfp_c2_ab_i2c: i2c at 6 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <6>;
++ };
++ };
++
++ i2c-switch at 77 {
++ compatible = "nxp,pca9547";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x77>;
++ i2c-mux-idle-disconnect;
++
++ twins_sfp_c2_bt_i2c: i2c at 1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++ };
++
++ twins_sfp_c2_bb_i2c: i2c at 2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++ };
++
++ twins_sfp_c3_at_i2c: i2c at 3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++ };
++
++ twins_sfp_c3_ab_i2c: i2c at 4 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <4>;
++ };
++
++ twins_sfp_c3_bt_i2c: i2c at 5 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <5>;
++ };
++
++ twins_sfp_c3_bb_i2c: i2c at 6 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <6>;
++ };
++ };
++
++ expander0: gpio-expander at 20 {
++ compatible = "nxp,pca9555";
++ gpio-controller;
++ #gpio-cells = <2>;
++ reg = <0x20>;
++ };
++
++ expander1: gpio-expander at 21 {
++ compatible = "nxp,pca9555";
++ gpio-controller;
++ #gpio-cells = <2>;
++ reg = <0x21>;
++ };
++
++ /* Half twins configuration; take over c3 from the other twin side */
++ i2c-switch at 73 {
++ compatible = "nxp,pca9547";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x73>;
++ i2c-mux-idle-disconnect;
++
++ htwins_sfp_c3_at_i2c: i2c at 3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++ };
++
++ htwins_sfp_c3_ab_i2c: i2c at 4 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <4>;
++ };
++
++ htwins_sfp_c3_bt_i2c: i2c at 5 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <5>;
++ };
++
++ htwins_sfp_c3_bb_i2c: i2c at 6 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <6>;
++ };
++ };
++
++ expander2: gpio-expander at 24 {
++ compatible = "nxp,pca9555";
++ gpio-controller;
++ #gpio-cells = <2>;
++ reg = <0x24>;
++ };
++
++ expander3: gpio-expander at 25 {
++ compatible = "nxp,pca9555";
++ gpio-controller;
++ #gpio-cells = <2>;
++ reg = <0x25>;
++ };
++};
++
++/* SD1 lanes #0.. #7 */
++&dpmac3 {
++ sfp = <&c1_at_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_c1_at>;
++};
++
++&dpmac4 {
++ sfp = <&c1_bt_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_c1_bt>;
++};
++
++&dpmac5 {
++ sfp = <&ht_c3_bt_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_ht_c3_bt>;
++};
++
++&dpmac6 {
++ sfp = <&ht_c3_at_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_ht_c3_at>;
++};
++
++&dpmac7 {
++ sfp = <&c2_at_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_c2_at>;
++};
++
++&dpmac8 {
++ sfp = <&c2_bt_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_c2_bt>;
++};
++
++&dpmac9 {
++ sfp = <&c3_at_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_c3_at>;
++};
++
++&dpmac10 {
++ sfp = <&c3_bt_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_c3_bt>;
++};
++
++/* SD2 lanes #0.. #7 */
++&dpmac11 {
++ sfp = <&ht_c3_ab_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_ht_c3_ab>;
++};
++
++&dpmac12 {
++ sfp = <&c1_ab_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_c1_ab>;
++};
++
++&dpmac13 { // ok
++ sfp = <&c3_ab_sfp>;
++ managed = "in-band-status";
++ phy-mode = "sgmii";
++ link-status-led = <&led_c3_ab>;
++};
++
++&dpmac14 { // ok
++ sfp = <&c3_bb_sfp>;
++ managed = "in-band-status";
++ phy-mode = "sgmii";
++ link-status-led = <&led_c3_bb>;
++};
++
++&dpmac15 {
++ sfp = <&ht_c3_bb_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_ht_c3_bb>;
++};
++
++&dpmac16 {
++ sfp = <&c2_bb_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_c2_bb>;
++};
++
++&dpmac17 {
++ /delete-property/ phy-handle;
++ /delete-property/ phy-connection-type;
++ sfp = <&c1_bb_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_c1_bb>;
++};
++
++&dpmac18 {
++ sfp = <&c2_ab_sfp>;
++ managed = "in-band-status";
++ link-status-led = <&led_c2_ab>;
++};
++
++&esdhc0 {
++ sd-uhs-sdr104;
++ sd-uhs-sdr50;
++ sd-uhs-sdr25;
++ sd-uhs-sdr12;
++ no-1-v-8;
++ status = "okay";
++};
++
++&pcs_mdio3 {
++ status = "okay";
++};
++
++&pcs_mdio4 {
++ status = "okay";
++};
++
++&pcs_mdio5 {
++ status = "okay";
++};
++
++&pcs_mdio6 {
++ status = "okay";
++};
++
++&pcs_mdio7 {
++ status = "okay";
++};
++
++&pcs_mdio8 {
++ status = "okay";
++};
++
++&pcs_mdio9 {
++ status = "okay";
++};
++
++&pcs_mdio10 {
++ status = "okay";
++};
++
++&pcs_mdio11 {
++ status = "okay";
++};
++
++&pcs_mdio12 {
++ status = "okay";
++};
++
++&pcs_mdio13 {
++ status = "okay";
++};
++
++&pcs_mdio14 {
++ status = "okay";
++};
++
++&pcs_mdio15 {
++ status = "okay";
++};
++
++&pcs_mdio16 {
++ status = "okay";
++};
++
++&pcs_mdio17 {
++ status = "okay";
++};
++
++&pcs_mdio18 {
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&usb0 {
++ status = "okay";
++};
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 9b8a99f868b..64432d9f76b 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -62,6 +62,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+ CONFIG_DDR_ECC=y
+ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+ CONFIG_SYS_FSL_DDR_INTLV_256B=y
++CONFIG_DM_PCA953X=y
+ CONFIG_MPC8XXX_GPIO=y
+ CONFIG_DM_I2C=y
+ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0018-lib-optee-always-copy-optee-to-OS-DTB-regardless-if-.patch b/board/solidrun/lx2160acex7/patches/uboot/0018-lib-optee-always-copy-optee-to-OS-DTB-regardless-if-.patch
new file mode 100644
index 0000000000..dbb217e9db
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0018-lib-optee-always-copy-optee-to-OS-DTB-regardless-if-.patch
@@ -0,0 +1,56 @@
+From ef94c50ce8f609ab319aef9a15195ef25bc57602 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sun, 10 Aug 2025 12:27:10 +0200
+Subject: [PATCH] lib: optee: always copy optee to OS DTB regardless if already
+ present
+
+OS DTB can't know whether optee is present or not, regardless if it has
+been put there previously.
+
+Always patch OS DTB.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ lib/optee/optee.c | 19 ++++++-------------
+ 1 file changed, 6 insertions(+), 13 deletions(-)
+
+diff --git a/lib/optee/optee.c b/lib/optee/optee.c
+index 393f2715a9c..53a08370b73 100644
+--- a/lib/optee/optee.c
++++ b/lib/optee/optee.c
+@@ -80,9 +80,12 @@ static int optee_copy_firmware_node(ofnode node, void *fdt_blob)
+ return offs;
+ }
+
+- offs = fdt_add_subnode(fdt_blob, offs, "optee");
+- if (offs < 0)
+- return offs;
++ offs = fdt_path_offset(fdt_blob, "/firmware/optee");
++ if (offs < 0) {
++ offs = fdt_add_subnode(fdt_blob, offs, "optee");
++ if (offs < 0)
++ return offs;
++ }
+
+ /* copy the compatible property */
+ prop = ofnode_get_property(node, "compatible", &len);
+@@ -125,16 +128,6 @@ int optee_copy_fdt_nodes(void *new_blob)
+ return 0;
+ }
+
+- /*
+- * Do not proceed if the target dt already has an OP-TEE node.
+- * In this case assume that the system knows better somehow,
+- * so do not interfere.
+- */
+- if (fdt_path_offset(new_blob, "/firmware/optee") >= 0) {
+- debug("OP-TEE Device Tree node already exists in target");
+- return 0;
+- }
+-
+ ret = optee_copy_firmware_node(node, new_blob);
+ if (ret < 0) {
+ printf("Failed to add OP-TEE firmware node\n");
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0019-board-solidrun-lx2160cex7-fix-xspi-flash-compatible-.patch b/board/solidrun/lx2160acex7/patches/uboot/0019-board-solidrun-lx2160cex7-fix-xspi-flash-compatible-.patch
new file mode 100644
index 0000000000..e333a5dd48
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0019-board-solidrun-lx2160cex7-fix-xspi-flash-compatible-.patch
@@ -0,0 +1,30 @@
+From 01418030bef11425c956caaff185e08e34ce4553 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sun, 10 Aug 2025 15:56:54 +0200
+Subject: [PATCH] board: solidrun: lx2160cex7: fix xspi flash compatible string
+
+The SPI nor flash on LX2160A CEX-7 is not an m25p80 but MT35.
+Fi the device-tree compatible string to use jedec ids and automatic
+identification.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ arch/arm/dts/fsl-lx2160a-cex7.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dtsi b/arch/arm/dts/fsl-lx2160a-cex7.dtsi
+index e4b72707081..fa5bae4d796 100644
+--- a/arch/arm/dts/fsl-lx2160a-cex7.dtsi
++++ b/arch/arm/dts/fsl-lx2160a-cex7.dtsi
+@@ -165,7 +165,7 @@
+ flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+- compatible = "micron,m25p80";
++ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0020-board-solidrun-lx2160acex7-fix-serdes-lane-dpmac-swa.patch b/board/solidrun/lx2160acex7/patches/uboot/0020-board-solidrun-lx2160acex7-fix-serdes-lane-dpmac-swa.patch
new file mode 100644
index 0000000000..4a7ec79d95
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0020-board-solidrun-lx2160acex7-fix-serdes-lane-dpmac-swa.patch
@@ -0,0 +1,124 @@
+From 54e0af56a7f7b87fd1da202a296d10e7037bc000 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sun, 24 Aug 2025 16:31:56 +0200
+Subject: [PATCH] board: solidrun: lx2160acex7: fix serdes lane dpmac swap
+
+SerDes lane numbering and protocol converter register bitfield names are
+inconsistent on LX2160 for SerDes #1.
+
+E.g. 10G Protocol converter Port C is SD1 lane F (number 2) dpmac 5.
+
+Swap the dpmacs in lookup tables so that correct speed and status are
+configured during board_fix_fdt.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ board/solidrun/lx2160acex7/serdes.c | 32 ++++++++++++++---------------
+ 1 file changed, 16 insertions(+), 16 deletions(-)
+
+diff --git a/board/solidrun/lx2160acex7/serdes.c b/board/solidrun/lx2160acex7/serdes.c
+index c6b6d9bbfdc..c62a54d1681 100644
+--- a/board/solidrun/lx2160acex7/serdes.c
++++ b/board/solidrun/lx2160acex7/serdes.c
+@@ -150,82 +150,82 @@ static void board_fix_fdt_macs(void *fdt) {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIA_CFG,
+ .mode = "sgmii",
+- .mac = DPMAC3,
++ .mac = DPMAC10,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIB_CFG,
+ .mode = "sgmii",
+- .mac = DPMAC4,
++ .mac = DPMAC9,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIC_CFG,
+ .mode = "sgmii",
+- .mac = DPMAC5,
++ .mac = DPMAC8,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+ .pcr_ena_mask = LYNX_28G_PCC8_SGMIID_CFG,
+ .mode = "sgmii",
+- .mac = DPMAC6,
++ .mac = DPMAC7,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIE_CFG,
+ .mode = "sgmii",
+- .mac = DPMAC7,
++ .mac = DPMAC6,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIF_CFG,
+ .mode = "sgmii",
+- .mac = DPMAC8,
++ .mac = DPMAC5,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIG_CFG,
+ .mode = "sgmii",
+- .mac = DPMAC9,
++ .mac = DPMAC4,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIH_CFG,
+ .mode = "sgmii",
+- .mac = DPMAC10,
++ .mac = DPMAC3,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIA_CFG,
+ .mode = "xgmii",
+- .mac = DPMAC3,
++ .mac = DPMAC10,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIB_CFG,
+ .mode = "xgmii",
+- .mac = DPMAC4,
++ .mac = DPMAC9,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIC_CFG,
+ .mode = "xgmii",
+- .mac = DPMAC5,
++ .mac = DPMAC8,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIID_CFG,
+ .mode = "xgmii",
+- .mac = DPMAC6,
++ .mac = DPMAC7,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIE_CFG,
+ .mode = "xgmii",
+- .mac = DPMAC7,
++ .mac = DPMAC6,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIF_CFG,
+ .mode = "xgmii",
+- .mac = DPMAC8,
++ .mac = DPMAC5,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIG_CFG,
+ .mode = "xgmii",
+- .mac = DPMAC9,
++ .mac = DPMAC4,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIH_CFG,
+ .mode = "xgmii",
+- .mac = DPMAC10,
++ .mac = DPMAC3,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
+ .pcr_ena_mask = LYNX_28G_PCCD_E25GA_CFG,
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0021-lib-optee-fix-adding-optee-subnode-if-not-present.patch b/board/solidrun/lx2160acex7/patches/uboot/0021-lib-optee-fix-adding-optee-subnode-if-not-present.patch
new file mode 100644
index 0000000000..cf5039eec6
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0021-lib-optee-fix-adding-optee-subnode-if-not-present.patch
@@ -0,0 +1,31 @@
+From 843be8bb55370449e0b331a84e0b99dc89b4edb4 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Mon, 25 Aug 2025 12:47:18 +0200
+Subject: [PATCH] lib: optee: fix adding optee subnode if not present
+
+OS DTB may or may not have /firmware/optee node.
+After probing for the node, offs variable was -1 and no longer pointing
+to the /firmware node.
+Re-initialise it before trying to create subnode optee under /firmware.
+
+Fixes: "lib: optee: always copy optee to OS DTB regardless if already present"
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ lib/optee/optee.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/lib/optee/optee.c b/lib/optee/optee.c
+index 53a08370b73..bfdce258a38 100644
+--- a/lib/optee/optee.c
++++ b/lib/optee/optee.c
+@@ -82,6 +82,7 @@ static int optee_copy_firmware_node(ofnode node, void *fdt_blob)
+
+ offs = fdt_path_offset(fdt_blob, "/firmware/optee");
+ if (offs < 0) {
++ offs = fdt_path_offset(fdt_blob, "/firmware");
+ offs = fdt_add_subnode(fdt_blob, offs, "optee");
+ if (offs < 0)
+ return offs;
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0022-board-solidrun-lx2160cex7-setup-retimers-for-active-.patch b/board/solidrun/lx2160acex7/patches/uboot/0022-board-solidrun-lx2160cex7-setup-retimers-for-active-.patch
new file mode 100644
index 0000000000..52a8e7d171
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0022-board-solidrun-lx2160cex7-setup-retimers-for-active-.patch
@@ -0,0 +1,513 @@
+From e37c29a62535fa9e57bd3a0a31f616fcdbbae36f Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Mon, 25 Aug 2025 14:54:38 +0200
+Subject: [PATCH 22/23] board: solidrun: lx2160cex7: setup retimers for active
+ configuration
+
+LX2160 Clearfog-CX and LX2162 Clearfog boards have retimers to support
+25Gbps speed on some serdes lanes.
+
+Configure the retimer during boot according to current active speed of
+the various macs.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ board/solidrun/lx2160acex7/Makefile | 1 +
+ board/solidrun/lx2160acex7/lx2160a.c | 3 +
+ board/solidrun/lx2160acex7/retimer.c | 458 +++++++++++++++++++++++++++
+ 3 files changed, 462 insertions(+)
+ create mode 100644 board/solidrun/lx2160acex7/retimer.c
+
+diff --git a/board/solidrun/lx2160acex7/Makefile b/board/solidrun/lx2160acex7/Makefile
+index a4bcd539cf8..9fe2b10310e 100644
+--- a/board/solidrun/lx2160acex7/Makefile
++++ b/board/solidrun/lx2160acex7/Makefile
+@@ -8,4 +8,5 @@
+ obj-y += lx2160a.o
+ obj-y += ddr.o
+ obj-$(CONFIG_TARGET_LX2160ACEX7) += eth_lx2160acex7.o
++obj-y += retimer.o
+ obj-y += serdes.o
+diff --git a/board/solidrun/lx2160acex7/lx2160a.c b/board/solidrun/lx2160acex7/lx2160a.c
+index 76302e8e568..dbfb1dc9d4d 100644
+--- a/board/solidrun/lx2160acex7/lx2160a.c
++++ b/board/solidrun/lx2160acex7/lx2160a.c
+@@ -211,8 +211,11 @@ static int setup_fan_ctrl(void) {
+ return ret;
+ }
+
++int setup_retimers(void);
++
+ int fsl_board_late_init(void) {
+ setup_fan_ctrl();
++ setup_retimers();
+
+ return 0;
+ }
+diff --git a/board/solidrun/lx2160acex7/retimer.c b/board/solidrun/lx2160acex7/retimer.c
+new file mode 100644
+index 00000000000..30f9863ce1f
+--- /dev/null
++++ b/board/solidrun/lx2160acex7/retimer.c
+@@ -0,0 +1,458 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2022-2025 Josua Mayer <josua at solid-run.com>
++ *
++ */
++
++#include <dm/device.h>
++#include <dm/ofnode.h>
++#include <dm/read.h>
++#include <dm/uclass.h>
++#include <i2c.h>
++
++#define ds250dfx10_write_register(dev, addr, val, mask) dm_i2c_reg_clrset(dev, addr, mask, val)
++
++static void ds250dfx10_config_1g(struct udevice *dev, uint8_t channel)
++{
++ int ret = 0;
++
++ // enable smbus access to single channel
++ ret |= ds250dfx10_write_register(dev, 0xFF, 0x01, 0x03);
++
++ // select channel
++ ret |= ds250dfx10_write_register(dev, 0xFC, 1 << channel, 0xFF);
++
++ // reset channel registers
++ ret |= ds250dfx10_write_register(dev, 0x00, 0x04, 0x04);
++
++ // assert cdr
++ ret |= ds250dfx10_write_register(dev, 0x0A, 0x0C, 0x0C);
++
++ // set manual data rate override to 1.25Gbps
++ ret |= ds250dfx10_write_register(dev, 0x60, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(dev, 0x61, 0xb2, 0xFF);
++ ret |= ds250dfx10_write_register(dev, 0x62, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(dev, 0x63, 0xb2, 0xFF);
++
++ // set maximum ppm delta tolerance
++ ret |= ds250dfx10_write_register(dev, 0x64, 0xFF, 0xFF);
++
++ // enable manual divider override
++ ret |= ds250dfx10_write_register(dev, 0x09, 0x04, 0x04);
++
++ // set divider to 16
++ ret |= ds250dfx10_write_register(dev, 0x18, 0x40, 0x70);
++
++ // enable pre- and post-fir
++ ret |= ds250dfx10_write_register(dev, 0x3D, 0x80, 0x80);
++
++ // set main cursor magnitude +15
++ ret |= ds250dfx10_write_register(dev, 0x3D, 0x00, 0x40);
++ ret |= ds250dfx10_write_register(dev, 0x3D, 0x0F, 0x1F);
++
++ // set pre cursor magnitude -4
++ ret |= ds250dfx10_write_register(dev, 0x3E, 0x40, 0x40);
++ ret |= ds250dfx10_write_register(dev, 0x3E, 0x04, 0x0F);
++
++ // set post cursor magnitude -4
++ ret |= ds250dfx10_write_register(dev, 0x3F, 0x40, 0x40);
++ ret |= ds250dfx10_write_register(dev, 0x3F, 0x04, 0x0F);
++
++ // deassert cdr
++ ret |= ds250dfx10_write_register(dev, 0x0A, 0x00, 0x0C);
++
++ if (!ret)
++ debug("failed to configure channel %u for 1G\n", channel);
++}
++
++static void ds250dfx10_config_10g(struct udevice *dev, uint8_t channel)
++{
++ int ret = 0;
++
++ // enable smbus access to single channel
++ ret |= ds250dfx10_write_register(dev, 0xFF, 0x01, 0x03);
++
++ // select channel
++ ret |= ds250dfx10_write_register(dev, 0xFC, 1 << channel, 0xFF);
++
++ // reset channel registers
++ ret |= ds250dfx10_write_register(dev, 0x00, 0x04, 0x04);
++
++ // assert cdr
++ ret |= ds250dfx10_write_register(dev, 0x0A, 0x0C, 0x0C);
++
++ // disable manual data rate override
++ ret |= ds250dfx10_write_register(dev, 0x60, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(dev, 0x61, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(dev, 0x62, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(dev, 0x63, 0x00, 0xFF);
++
++ // set minimum ppm delta tolerance (reset-default)
++ ret |= ds250dfx10_write_register(dev, 0x64, 0x00, 0xFF);
++
++ // disable manual divider override
++ ret |= ds250dfx10_write_register(dev, 0x09, 0x00, 0x04);
++
++ // select 10.3125 rate
++ ret |= ds250dfx10_write_register(dev, 0x2F, 0x00, 0xF0);
++
++ // enable pre- and post-fir
++ ret |= ds250dfx10_write_register(dev, 0x3D, 0x80, 0x80);
++
++ // set main cursor magnitude +15
++ ret |= ds250dfx10_write_register(dev, 0x3D, 0x00, 0x40);
++ ret |= ds250dfx10_write_register(dev, 0x3D, 0x0F, 0x1F);
++
++ // set pre cursor magnitude -4
++ ret |= ds250dfx10_write_register(dev, 0x3E, 0x40, 0x40);
++ ret |= ds250dfx10_write_register(dev, 0x3E, 0x04, 0x0F);
++
++ // set post cursor magnitude -4
++ ret |= ds250dfx10_write_register(dev, 0x3F, 0x40, 0x40);
++ ret |= ds250dfx10_write_register(dev, 0x3F, 0x04, 0x0F);
++
++ // deassert cdr
++ ret |= ds250dfx10_write_register(dev, 0x0A, 0x00, 0x0C);
++
++ if (!ret)
++ debug("failed to configure channel %u for 10G\n", channel);
++}
++
++static void ds250dfx10_config_25g(struct udevice *dev, uint8_t channel)
++{
++ int ret = 0;
++
++ // enable smbus access to single channel
++ ret |= ds250dfx10_write_register(dev, 0xFF, 0x01, 0x03);
++
++ // select channel
++ ret |= ds250dfx10_write_register(dev, 0xFC, 1 << channel, 0xFF);
++
++ // reset channel registers
++ ret |= ds250dfx10_write_register(dev, 0x00, 0x04, 0x04);
++
++ // assert cdr
++ ret |= ds250dfx10_write_register(dev, 0x0A, 0x0C, 0x0C);
++
++ // disable manual data rate override
++ ret |= ds250dfx10_write_register(dev, 0x60, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(dev, 0x61, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(dev, 0x62, 0x00, 0xFF);
++ ret |= ds250dfx10_write_register(dev, 0x63, 0x00, 0xFF);
++
++ // set minimum ppm delta tolerance (reset-default)
++ ret |= ds250dfx10_write_register(dev, 0x64, 0x00, 0xFF);
++
++ // disable manual divider override
++ ret |= ds250dfx10_write_register(dev, 0x09, 0x00, 0x04);
++
++ // select 25.78125 rate
++ ret |= ds250dfx10_write_register(dev, 0x2F, 0x50, 0xF0);
++
++ // enable pre- and post-fir
++ ret |= ds250dfx10_write_register(dev, 0x3D, 0x80, 0x80);
++
++ // set main cursor magnitude +15
++ ret |= ds250dfx10_write_register(dev, 0x3D, 0x00, 0x40);
++ ret |= ds250dfx10_write_register(dev, 0x3D, 0x0F, 0x1F);
++
++ // set pre cursor magnitude -4
++ ret |= ds250dfx10_write_register(dev, 0x3E, 0x40, 0x40);
++ ret |= ds250dfx10_write_register(dev, 0x3E, 0x04, 0x0F);
++
++ // set post cursor magnitude -4
++ ret |= ds250dfx10_write_register(dev, 0x3F, 0x40, 0x40);
++ ret |= ds250dfx10_write_register(dev, 0x3F, 0x04, 0x0F);
++
++ // deassert cdr
++ ret |= ds250dfx10_write_register(dev, 0x0A, 0x00, 0x0C);
++
++ if (ret)
++ debug("failed to configure channel %u for 25G\n", channel);
++}
++
++static int ds250dfx10_phy_set_mode(struct udevice *dev, uint8_t channel, const phy_interface_t submode)
++{
++ switch (submode) {
++ case PHY_INTERFACE_MODE_SGMII:
++ ds250dfx10_config_1g(dev, channel);
++ break;
++ case PHY_INTERFACE_MODE_10GBASER:
++ ds250dfx10_config_10g(dev, channel);
++ break;
++ case PHY_INTERFACE_MODE_25GBASER:
++ ds250dfx10_config_25g(dev, channel);
++ break;
++#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
++ case PHY_INTERFACE_MODE_XLAUI:
++ ds250dfx10_config_10g(dev, channel);
++ break;
++ case PHY_INTERFACE_MODE_25G_AUI:
++ case PHY_INTERFACE_MODE_CAUI2:
++ case PHY_INTERFACE_MODE_CAUI4:
++ ds250dfx10_config_25g(dev, channel);
++ break;
++#endif
++ default:
++ debug("unsupported interface submode %s\n", phy_string_for_interface(submode));
++ return -EOPNOTSUPP;
++ }
++
++ return 0;
++}
++
++enum {
++ DPMAC1 = 0,
++ DPMAC2,
++ DPMAC3,
++ DPMAC4,
++ DPMAC5,
++ DPMAC6,
++ DPMAC7,
++ DPMAC8,
++ DPMAC9,
++ DPMAC10,
++ DPMAC11,
++ DPMAC12,
++ DPMAC13,
++ DPMAC14,
++ DPMAC15,
++ DPMAC16,
++ DPMAC17,
++ DPMAC18,
++ DPMAC_MAX
++};
++
++static const char *const macs[] = {
++ "/fsl-mc at 80c000000/dpmacs/dpmac at 1",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at 2",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at 3",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at 4",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at 5",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at 6",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at 7",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at 8",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at 9",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at a",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at b",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at c",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at d",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at e",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at f",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at 10",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at 11",
++ "/fsl-mc at 80c000000/dpmacs/dpmac at 12",
++};
++
++static const char *const lx2160a_cex7_clearfog_cx = "solidrun,clearfog-cx";
++static const char *const lx2162a_som_clearfog = "lx2162a-clearfog";
++static const char *const lx2160a_i2c0_cex7_smb = "i2c at 2000000->i2c-mux at 77->i2c at 3";
++static const char *const lx2160a_i2c2 = "i2c at 2020000";
++
++/* configure retimers according to active network interface configuration */
++int setup_retimers(void) {
++ int ret = -ENODEV;
++ ofnode node;
++ phy_interface_t mode;
++ struct udevice *bus, *dev;
++
++ struct {
++ const char *const machine;
++ const unsigned int mac;
++ struct {
++ const char *const bus;
++ const uint8_t addr;
++ const uint8_t channel_mask;
++ } retimer[2];
++ const phy_interface_t mode;
++ } configs[] = {
++ { /* lx2160 clearfog-cx dpmac1 @ 40G qsfp 4 lanes */
++ .machine = lx2160a_cex7_clearfog_cx,
++ .mac = DPMAC1,
++ .retimer = {
++ { /* tx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x22,
++ .channel_mask = (1U << 0) | (1U << 1) | (1U << 2) | (1U << 3),
++ }, { /* rx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x23,
++ .channel_mask = (1U << 0) | (1U << 1) | (1U << 2) | (1U << 3),
++ }
++ },
++ .mode = PHY_INTERFACE_MODE_XLAUI,
++ }, { /* lx2160 clearfog-cx dpmac1 @ 100G qsfp 4 lanes */
++ .machine = lx2160a_cex7_clearfog_cx,
++ .mac = DPMAC1,
++ .retimer = {
++ { /* tx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x22,
++ .channel_mask = (1U << 0) | (1U << 1) | (1U << 2) | (1U << 3),
++ }, { /* rx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x23,
++ .channel_mask = (1U << 0) | (1U << 1) | (1U << 2) | (1U << 3),
++ }
++ },
++ .mode = PHY_INTERFACE_MODE_CAUI4,
++ }, { /* lx2160 clearfog-cx dpmac1 @ 50G qsfp 2 lanes */
++ .machine = lx2160a_cex7_clearfog_cx,
++ .mac = DPMAC1,
++ .retimer = {
++ { /* tx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x22,
++ .channel_mask = (1U << 2) | (1U << 3),
++ }, { /* rx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x23,
++ .channel_mask = (1U << 2) | (1U << 3),
++ }
++ },
++ .mode = PHY_INTERFACE_MODE_CAUI2,
++ }, { /* lx2160 clearfog-cx dpmac2 @ 50G qsfp 2 lanes */
++ .machine = lx2160a_cex7_clearfog_cx,
++ .mac = DPMAC2,
++ .retimer = {
++ { /* tx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x22,
++ .channel_mask = (1U << 0) | (1U << 1),
++ }, { /* rx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x23,
++ .channel_mask = (1U << 0) | (1U << 1),
++ }
++ },
++ .mode = PHY_INTERFACE_MODE_CAUI2,
++ }, { /* lx2160 clearfog-cx dpmac6 */
++ .machine = lx2160a_cex7_clearfog_cx,
++ .mac = DPMAC6,
++ .retimer = {
++ { /* tx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x22,
++ .channel_mask = (1U << 0),
++ }, { /* rx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x23,
++ .channel_mask = (1U << 0),
++ }
++ },
++ }, { /* lx2160 clearfog-cx dpmac5 */
++ .machine = lx2160a_cex7_clearfog_cx,
++ .mac = DPMAC5,
++ .retimer = {
++ { /* tx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x22,
++ .channel_mask = (1U << 1),
++ }, { /* rx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x23,
++ .channel_mask = (1U << 1),
++ }
++ },
++ }, { /* lx2160 clearfog-cx dpmac4 */
++ .machine = lx2160a_cex7_clearfog_cx,
++ .mac = DPMAC4,
++ .retimer = {
++ { /* tx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x22,
++ .channel_mask = (1U << 2),
++ }, { /* rx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x23,
++ .channel_mask = (1U << 2),
++ }
++ },
++ }, { /* lx2160 clearfog-cx dpmac3 tx */
++ .machine = lx2160a_cex7_clearfog_cx,
++ .mac = DPMAC3,
++ .retimer = {
++ { /* tx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x22,
++ .channel_mask = (1U << 3),
++ }, { /* rx */
++ .bus = lx2160a_i2c0_cex7_smb,
++ .addr = 0x23,
++ .channel_mask = (1U << 3),
++ }
++ },
++ }, { /* lx2162 clearfog dpmac6 tx */
++ .machine = lx2162a_som_clearfog,
++ .mac = DPMAC6,
++ .retimer = {
++ { /* tx */
++ .bus = lx2160a_i2c2,
++ .addr = 0x18,
++ .channel_mask = (1U << 0),
++ }, { /* rx */
++ .bus = lx2160a_i2c2,
++ .addr = 0x18,
++ .channel_mask = (1U << 1),
++ }
++ },
++ }, { /* lx2162 clearfog dpmac5 tx */
++ .machine = lx2162a_som_clearfog,
++ .mac = DPMAC5,
++ .retimer = {
++ { /* tx */
++ .bus = lx2160a_i2c2,
++ .addr = 0x18,
++ .channel_mask = (1U << 2),
++ }, { /* rx */
++ .bus = lx2160a_i2c2,
++ .addr = 0x18,
++ .channel_mask = (1U << 3),
++ }
++ },
++ },
++ };
++
++ for (int i = 0; i < ARRAY_SIZE(configs); i++) {
++ if (!of_machine_is_compatible(configs[i].machine))
++ continue;
++
++ node = ofnode_path(macs[configs[i].mac]);
++ if (!ofnode_valid(node))
++ continue;
++
++ mode = ofnode_read_phy_mode(node);
++ if (mode == PHY_INTERFACE_MODE_NA)
++ continue;
++
++ if ((configs[i].mode != PHY_INTERFACE_MODE_NA) && (mode != configs[i].mode))
++ continue;
++
++ for (int j = 0; j < 2; j++) {
++ for (int k = 0; k < 8; k++) {
++ if (!(configs[i].retimer[j].channel_mask & (1 << k)))
++ continue;
++
++ ret = uclass_get_device_by_name(UCLASS_I2C, configs[i].retimer[j].bus, &bus);
++ if (ret) {
++ printf("failed to get i2c bus %s: %d\n", configs[i].retimer[j].bus, ret);
++ return ret;
++ }
++
++ ret = i2c_get_chip(bus, configs[i].retimer[j].addr, 1, &dev);
++ if (ret) {
++ printf("failed to get %s->retimer@%x: %d\n", configs[i].retimer[j].bus, configs[i].retimer[j].addr, ret);
++ return ret;
++ }
++
++ ret = ds250dfx10_phy_set_mode(dev, k, mode);
++ if (ret) {
++ printf("failed to configure %s->retimer@%x channel %u for %s: %d\n", configs[i].retimer[j].bus, configs[i].retimer[j].addr, k, phy_string_for_interface(mode), ret);
++ return ret;
++ }
++ }
++ }
++ }
++
++ return ret;
++}
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0023-board-solidrun-disable-some-unused-config-options.patch b/board/solidrun/lx2160acex7/patches/uboot/0023-board-solidrun-disable-some-unused-config-options.patch
new file mode 100644
index 0000000000..d19aaefb18
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0023-board-solidrun-disable-some-unused-config-options.patch
@@ -0,0 +1,66 @@
+From 730de8472646472408611b394e94f797252ab27d Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Tue, 12 Aug 2025 14:55:25 +0200
+Subject: [PATCH 23/23] board: solidrun: disable some unused config options
+
+---
+ configs/lx2160acex7_tfa_defconfig | 9 +--------
+ 1 file changed, 1 insertion(+), 8 deletions(-)
+
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 64432d9f76b..461abb76af2 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -33,13 +33,9 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2
+ CONFIG_DEFAULT_FDT_FILE="freescale/fsl-lx2160a-clearfog-cx.dtb"
+ CONFIG_SYS_PBSIZE=532
+ CONFIG_CMD_TLV_EEPROM=y
+-CONFIG_CMD_GREPENV=y
+-CONFIG_CMD_EEPROM=y
+-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
+ CONFIG_CMD_DM=y
+ CONFIG_CMD_GPIO=y
+-CONFIG_CMD_GPT=y
+ CONFIG_CMD_I2C=y
+ CONFIG_CMD_MMC=y
+ CONFIG_CMD_OPTEE_RPMB=y
+@@ -47,7 +43,6 @@ CONFIG_CMD_PCI=y
+ CONFIG_CMD_POWEROFF=y
+ CONFIG_CMD_USB=y
+ CONFIG_CMD_WDT=y
+-CONFIG_CMD_CACHE=y
+ CONFIG_OF_CONTROL=y
+ CONFIG_ENV_OVERWRITE=y
+ CONFIG_ENV_IS_IN_MMC=y
+@@ -72,13 +67,11 @@ CONFIG_I2C_EEPROM=y
+ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
+ CONFIG_SUPPORT_EMMC_RPMB=y
+ CONFIG_SUPPORT_EMMC_BOOT=y
+-CONFIG_MMC_HS400_SUPPORT=y
+ CONFIG_FSL_ESDHC=y
+ CONFIG_MTD=y
+ CONFIG_DM_SPI_FLASH=y
+ CONFIG_SPI_FLASH_STMICRO=y
+ CONFIG_SPI_FLASH_MT35XU=y
+-CONFIG_SPI_FLASH_WINBOND=y
+ # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+ CONFIG_PHYLIB=y
+ CONFIG_PHY_AQUANTIA=y
+@@ -87,7 +80,6 @@ CONFIG_PHY_MARVELL_10G=y
+ CONFIG_FSL_MEMAC=y
+ CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
+ CONFIG_DM_ETH_PHY=y
+-CONFIG_E1000=y
+ CONFIG_MII=y
+ CONFIG_NVME_PCI=y
+ CONFIG_PCIE_LAYERSCAPE_RC=y
+@@ -108,4 +100,5 @@ CONFIG_USB_XHCI_DWC3=y
+ CONFIG_USB_MAX_CONTROLLER_COUNT=2
+ CONFIG_WDT=y
+ CONFIG_WDT_SBSA=y
++# CONFIG_FAT_WRITE is not set
+ CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0024-board-solidrun-lx2160acex7-fix-various-mistakes-in-s.patch b/board/solidrun/lx2160acex7/patches/uboot/0024-board-solidrun-lx2160acex7-fix-various-mistakes-in-s.patch
new file mode 100644
index 0000000000..3fc7a6613d
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0024-board-solidrun-lx2160acex7-fix-various-mistakes-in-s.patch
@@ -0,0 +1,703 @@
+From a5f43e23c745093b58b2df1dce0cad0580fba6fc Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Wed, 27 Aug 2025 12:31:04 +0200
+Subject: [PATCH 24/25] board: solidrun: lx2160acex7: fix various mistakes in
+ serdes #2 regs
+
+1. The protocol converter register bitfield names and dpmac numbers are
+ inconsistent on LX2160 SerDes #2.
+
+ In particular on SerDes #2:
+ - 1G protocol converter port A is lane A (number 0) dpmac 11
+ - 1G protocol converter port E is lane E (number 4) dpmac 15
+ - 10G protocol converter port G is lane G (number 6) dpmac 13
+ - 10G protocol converter port H is lane H (number 7) dpmac 14
+
+ Reorder the dpmacs in lookup tables so that correct speed and status
+ are configured during board_fix_fdt.
+
+2. SerDes #2 only supports 10G speeds on lanes G/H dpmac 13/14, and
+ does not support 25G speeds at all.
+
+ Remove code handling these configurations.
+
+3. Match the protocol converter configuration registers by value instead
+ of not-equal-zero so that configurations such as usxgmii/xfi can be
+ matched accurately.
+
+4. Add USXXGMII configurations. For now usxgmii is only enabled through
+ DPL, when starting Linux, hence for u-boot itself this changes
+ nothing.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ board/solidrun/lx2160acex7/serdes.c | 417 +++++++++++++++++-----------
+ 1 file changed, 253 insertions(+), 164 deletions(-)
+
+diff --git a/board/solidrun/lx2160acex7/serdes.c b/board/solidrun/lx2160acex7/serdes.c
+index c62a54d1681..8e19a471b04 100644
+--- a/board/solidrun/lx2160acex7/serdes.c
++++ b/board/solidrun/lx2160acex7/serdes.c
+@@ -6,62 +6,109 @@
+
+ #include <fdt_support.h>
+
++/* Devoce Configuration Register base address */
++#define DCFG_CCSR_BASE (void *)0x01E00000
++
+ /* SerDes base address */
+-#define LYNX_28G_SDn_BASE(block) ((void *)0x01EA0000 + (block) * 0x10000)
++#define LYNX_28G_SDn_BASE(block) (DCFG_CCSR_BASE + 0x000A0000 + (block) * 0x10000)
+
+ /* Protocol Configuration Register 0 */
+ #define LYNX_28G_PCC0 0x1080
+-#define LYNX_28G_PCC0_PEXA_CFG GENMASK(30, 28)
+-#define LYNX_28G_PCC0_PEXB_CFG GENMASK(26, 24)
++#define LYNX_28G_PCC0_PEXA_CFG_MASK GENMASK(30, 28)
++#define LYNX_28G_PCC0_PEXA_CFG(val) ((val << 28) & LYNX_28G_PCC0_PEXA_CFG_MASK)
++#define LYNX_28G_PCC0_PEXB_CFG_MASK GENMASK(26, 24)
++#define LYNX_28G_PCC0_PEXB_CFG(val) ((val << 24) & LYNX_28G_PCC0_PEXB_CFG_MASK)
+
+ /* Protocol Configuration Register 2 */
+ #define LYNX_28G_PCC2 0x1088
+-#define LYNX_28G_PCC2_SATAA_CFG GENMASK(30, 28)
+-#define LYNX_28G_PCC2_SATAB_CFG GENMASK(26, 24)
+-#define LYNX_28G_PCC2_SATAC_CFG GENMASK(22, 20)
+-#define LYNX_28G_PCC2_SATAD_CFG GENMASK(18, 16)
++#define LYNX_28G_PCC2_SATAA_CFG_MASK GENMASK(30, 28)
++#define LYNX_28G_PCC2_SATAA_CFG(val) ((val << 28) & LYNX_28G_PCC2_SATAA_CFG_MASK)
++#define LYNX_28G_PCC2_SATAB_CFG_MASK GENMASK(26, 24)
++#define LYNX_28G_PCC2_SATAB_CFG(val) ((val << 24) & LYNX_28G_PCC2_SATAB_CFG_MASK)
++#define LYNX_28G_PCC2_SATAC_CFG_MASK GENMASK(22, 20)
++#define LYNX_28G_PCC2_SATAC_CFG(val) ((val << 20) & LYNX_28G_PCC2_SATAC_CFG_MASK)
++#define LYNX_28G_PCC2_SATAD_CFG_MASK GENMASK(18, 16)
++#define LYNX_28G_PCC2_SATAD_CFG(val) ((val << 16) & LYNX_28G_PCC2_SATAD_CFG_MASK)
+
+ /* Protocol Configuration Register 8 */
+ #define LYNX_28G_PCC8 0x10A0
+-#define LYNX_28G_PCC8_SGMIIA_CFG GENMASK(30, 28)
+-#define LYNX_28G_PCC8_SGMIIB_CFG GENMASK(26, 24)
+-#define LYNX_28G_PCC8_SGMIIC_CFG GENMASK(22, 20)
+-#define LYNX_28G_PCC8_SGMIID_CFG GENMASK(18, 16)
+-#define LYNX_28G_PCC8_SGMIIE_CFG GENMASK(14, 12)
+-#define LYNX_28G_PCC8_SGMIIF_CFG GENMASK(10, 8)
+-#define LYNX_28G_PCC8_SGMIIG_CFG GENMASK(6, 4)
+-#define LYNX_28G_PCC8_SGMIIH_CFG GENMASK(2, 0)
++#define LYNX_28G_PCC8_SGMIIA_CFG_MASK GENMASK(30, 28)
++#define LYNX_28G_PCC8_SGMIIA_CFG(val) ((val << 28) & LYNX_28G_PCC8_SGMIIA_CFG_MASK)
++#define LYNX_28G_PCC8_SGMIIB_CFG_MASK GENMASK(26, 24)
++#define LYNX_28G_PCC8_SGMIIB_CFG(val) ((val << 24) & LYNX_28G_PCC8_SGMIIB_CFG_MASK)
++#define LYNX_28G_PCC8_SGMIIC_CFG_MASK GENMASK(22, 20)
++#define LYNX_28G_PCC8_SGMIIC_CFG(val) ((val << 20) & LYNX_28G_PCC8_SGMIIC_CFG_MASK)
++#define LYNX_28G_PCC8_SGMIID_CFG_MASK GENMASK(18, 16)
++#define LYNX_28G_PCC8_SGMIID_CFG(val) ((val << 16) & LYNX_28G_PCC8_SGMIID_CFG_MASK)
++#define LYNX_28G_PCC8_SGMIIE_CFG_MASK GENMASK(14, 12)
++#define LYNX_28G_PCC8_SGMIIE_CFG(val) ((val << 12) & LYNX_28G_PCC8_SGMIIE_CFG_MASK)
++#define LYNX_28G_PCC8_SGMIIF_CFG_MASK GENMASK(10, 8)
++#define LYNX_28G_PCC8_SGMIIF_CFG(val) ((val << 8) & LYNX_28G_PCC8_SGMIIF_CFG_MASK)
++#define LYNX_28G_PCC8_SGMIIG_CFG_MASK GENMASK(6, 4)
++#define LYNX_28G_PCC8_SGMIIG_CFG(val) ((val << 4) & LYNX_28G_PCC8_SGMIIG_CFG_MASK)
++#define LYNX_28G_PCC8_SGMIIH_CFG_MASK GENMASK(2, 0)
++#define LYNX_28G_PCC8_SGMIIH_CFG(val) ((val << 0) & LYNX_28G_PCC8_SGMIIH_CFG_MASK)
+
+ /* Protocol Configuration Register C */
+ #define LYNX_28G_PCCC 0x10B0
+-#define LYNX_28G_PCCC_SXGMIIA_CFG GENMASK(30, 28)
+-#define LYNX_28G_PCCC_SXGMIIB_CFG GENMASK(26, 24)
+-#define LYNX_28G_PCCC_SXGMIIC_CFG GENMASK(22, 20)
+-#define LYNX_28G_PCCC_SXGMIID_CFG GENMASK(18, 16)
+-#define LYNX_28G_PCCC_SXGMIIE_CFG GENMASK(14, 12)
+-#define LYNX_28G_PCCC_SXGMIIF_CFG GENMASK(10, 8)
+-#define LYNX_28G_PCCC_SXGMIIG_CFG GENMASK(6, 4)
+-#define LYNX_28G_PCCC_SXGMIIH_CFG GENMASK(2, 0)
++#define LYNX_28G_PCCC_SXGMIIA_XFI BIT(31)
++#define LYNX_28G_PCCC_SXGMIIA_CFG_MASK GENMASK(30, 28)
++#define LYNX_28G_PCCC_SXGMIIA_CFG(val) ((val << 28) & LYNX_28G_PCCC_SXGMIIA_CFG_MASK)
++#define LYNX_28G_PCCC_SXGMIIB_XFI BIT(27)
++#define LYNX_28G_PCCC_SXGMIIB_CFG_MASK GENMASK(26, 24)
++#define LYNX_28G_PCCC_SXGMIIB_CFG(val) ((val << 24) & LYNX_28G_PCCC_SXGMIIB_CFG_MASK)
++#define LYNX_28G_PCCC_SXGMIIC_XFI BIT(23)
++#define LYNX_28G_PCCC_SXGMIIC_CFG_MASK GENMASK(22, 20)
++#define LYNX_28G_PCCC_SXGMIIC_CFG(val) ((val << 20) & LYNX_28G_PCCC_SXGMIIC_CFG_MASK)
++#define LYNX_28G_PCCC_SXGMIID_XFI BIT(19)
++#define LYNX_28G_PCCC_SXGMIID_CFG_MASK GENMASK(18, 16)
++#define LYNX_28G_PCCC_SXGMIID_CFG(val) ((val << 16) & LYNX_28G_PCCC_SXGMIID_CFG_MASK)
++#define LYNX_28G_PCCC_SXGMIIE_XFI BIT(15)
++#define LYNX_28G_PCCC_SXGMIIE_CFG_MASK GENMASK(14, 12)
++#define LYNX_28G_PCCC_SXGMIIE_CFG(val) ((val << 12) & LYNX_28G_PCCC_SXGMIIE_CFG_MASK)
++#define LYNX_28G_PCCC_SXGMIIF_XFI BIT(11)
++#define LYNX_28G_PCCC_SXGMIIF_CFG_MASK GENMASK(10, 8)
++#define LYNX_28G_PCCC_SXGMIIF_CFG(val) ((val << 8) & LYNX_28G_PCCC_SXGMIIF_CFG_MASK)
++#define LYNX_28G_PCCC_SXGMIIG_XFI BIT(7)
++#define LYNX_28G_PCCC_SXGMIIG_CFG_MASK GENMASK(6, 4)
++#define LYNX_28G_PCCC_SXGMIIG_CFG(val) ((val << 4) & LYNX_28G_PCCC_SXGMIIG_CFG_MASK)
++#define LYNX_28G_PCCC_SXGMIIH_XFI BIT(3)
++#define LYNX_28G_PCCC_SXGMIIH_CFG_MASK GENMASK(2, 0)
++#define LYNX_28G_PCCC_SXGMIIH_CFG(val) ((val << 0) & LYNX_28G_PCCC_SXGMIIH_CFG_MASK)
+
+ /* Protocol Configuration Register D */
+ #define LYNX_28G_PCCD 0x10B4
+-#define LYNX_28G_PCCD_E25GA_CFG GENMASK(30, 28)
+-#define LYNX_28G_PCCD_E25GB_CFG GENMASK(26, 24)
+-#define LYNX_28G_PCCD_E25GC_CFG GENMASK(22, 20)
+-#define LYNX_28G_PCCD_E25GD_CFG GENMASK(18, 16)
+-#define LYNX_28G_PCCD_E25GE_CFG GENMASK(14, 12)
+-#define LYNX_28G_PCCD_E25GF_CFG GENMASK(10, 8)
+-#define LYNX_28G_PCCD_E25GG_CFG GENMASK(6, 4)
+-#define LYNX_28G_PCCD_E25GH_CFG GENMASK(2, 0)
++#define LYNX_28G_PCCD_E25GA_CFG_MASK GENMASK(30, 28)
++#define LYNX_28G_PCCD_E25GA_CFG(val) ((val << 28) & LYNX_28G_PCCD_E25GA_CFG_MASK)
++#define LYNX_28G_PCCD_E25GB_CFG_MASK GENMASK(26, 24)
++#define LYNX_28G_PCCD_E25GB_CFG(val) ((val << 24) & LYNX_28G_PCCD_E25GB_CFG_MASK)
++#define LYNX_28G_PCCD_E25GC_CFG_MASK GENMASK(22, 20)
++#define LYNX_28G_PCCD_E25GC_CFG(val) ((val << 20) & LYNX_28G_PCCD_E25GC_CFG_MASK)
++#define LYNX_28G_PCCD_E25GD_CFG_MASK GENMASK(18, 16)
++#define LYNX_28G_PCCD_E25GD_CFG(val) ((val << 16) & LYNX_28G_PCCD_E25GD_CFG_MASK)
++#define LYNX_28G_PCCD_E25GE_CFG_MASK GENMASK(14, 12)
++#define LYNX_28G_PCCD_E25GE_CFG(val) ((val << 12) & LYNX_28G_PCCD_E25GE_CFG_MASK)
++#define LYNX_28G_PCCD_E25GF_CFG_MASK GENMASK(10, 8)
++#define LYNX_28G_PCCD_E25GF_CFG(val) ((val << 8) & LYNX_28G_PCCD_E25GF_CFG_MASK)
++#define LYNX_28G_PCCD_E25GG_CFG_MASK GENMASK(6, 4)
++#define LYNX_28G_PCCD_E25GG_CFG(val) ((val << 4) & LYNX_28G_PCCD_E25GG_CFG_MASK)
++#define LYNX_28G_PCCD_E25GH_CFG_MASK GENMASK(2, 0)
++#define LYNX_28G_PCCD_E25GH_CFG(val) ((val << 0) & LYNX_28G_PCCD_E25GH_CFG_MASK)
+
+ /* Protocol Configuration Register E */
+ #define LYNX_28G_PCCE 0x10B8
+-#define LYNX_28G_PCCE_E40GA_CFG GENMASK(30, 28)
+-#define LYNX_28G_PCCE_E40GB_CFG GENMASK(26, 24)
+-#define LYNX_28G_PCCE_E50GA_CFG GENMASK(22, 20)
+-#define LYNX_28G_PCCE_E50GB_CFG GENMASK(18, 16)
+-#define LYNX_28G_PCCE_E100GA_CFG GENMASK(14, 12)
+-#define LYNX_28G_PCCE_E100GB_CFG GENMASK(10, 8)
++#define LYNX_28G_PCCE_E40GA_CFG_MASK GENMASK(30, 28)
++#define LYNX_28G_PCCE_E40GA_CFG(val) ((val << 28) & LYNX_28G_PCCE_E40GA_CFG_MASK)
++#define LYNX_28G_PCCE_E40GB_CFG_MASK GENMASK(26, 24)
++#define LYNX_28G_PCCE_E40GB_CFG(val) ((val << 24) & LYNX_28G_PCCE_E40GB_CFG_MASK)
++#define LYNX_28G_PCCE_E50GA_CFG_MASK GENMASK(22, 20)
++#define LYNX_28G_PCCE_E50GA_CFG(val) ((val << 20) & LYNX_28G_PCCE_E50GA_CFG_MASK)
++#define LYNX_28G_PCCE_E50GB_CFG_MASK GENMASK(18, 16)
++#define LYNX_28G_PCCE_E50GB_CFG(val) ((val << 16) & LYNX_28G_PCCE_E50GB_CFG_MASK)
++#define LYNX_28G_PCCE_E100GA_CFG_MASK GENMASK(14, 12)
++#define LYNX_28G_PCCE_E100GA_CFG(val) ((val << 12) & LYNX_28G_PCCE_E100GA_CFG_MASK)
++#define LYNX_28G_PCCE_E100GB_CFG_MASK GENMASK(10, 8)
++#define LYNX_28G_PCCE_E100GB_CFG(val) ((val << 8) & LYNX_28G_PCCE_E100GB_CFG_MASK)
+
+ /* Lane a General Control Register */
+ #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
+@@ -141,286 +188,317 @@ static void board_fix_fdt_macs(void *fdt) {
+ };
+
+ struct {
+- const u32 __iomem *pcr;
++ const u32 __iomem *const pcr;
+ const u32 pcr_ena_mask;
++ const u32 pcr_ena_val;
+ const char *const mode;
+ const unsigned int mac;
+ } ports[] = {
+ {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIA_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIA_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIA_CFG(1),
+ .mode = "sgmii",
+ .mac = DPMAC10,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIB_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIB_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIB_CFG(1),
+ .mode = "sgmii",
+ .mac = DPMAC9,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIC_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIC_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIC_CFG(1),
+ .mode = "sgmii",
+ .mac = DPMAC8,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIID_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIID_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIID_CFG(1),
+ .mode = "sgmii",
+ .mac = DPMAC7,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIE_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIE_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIE_CFG(1),
+ .mode = "sgmii",
+ .mac = DPMAC6,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIF_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIF_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIF_CFG(1),
+ .mode = "sgmii",
+ .mac = DPMAC5,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIG_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIG_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIG_CFG(1),
+ .mode = "sgmii",
+ .mac = DPMAC4,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIH_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIH_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIH_CFG(1),
+ .mode = "sgmii",
+ .mac = DPMAC3,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIA_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIA_CFG_MASK | LYNX_28G_PCCC_SXGMIIA_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIA_CFG(1) | LYNX_28G_PCCC_SXGMIIA_XFI,
+ .mode = "xgmii",
+ .mac = DPMAC10,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIB_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIB_CFG_MASK | LYNX_28G_PCCC_SXGMIIB_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIB_CFG(1) | LYNX_28G_PCCC_SXGMIIB_XFI,
+ .mode = "xgmii",
+ .mac = DPMAC9,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIC_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIC_CFG_MASK | LYNX_28G_PCCC_SXGMIIC_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIC_CFG(1) | LYNX_28G_PCCC_SXGMIIC_XFI,
+ .mode = "xgmii",
+ .mac = DPMAC8,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIID_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIID_CFG_MASK | LYNX_28G_PCCC_SXGMIID_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIID_CFG(1) | LYNX_28G_PCCC_SXGMIID_XFI,
+ .mode = "xgmii",
+ .mac = DPMAC7,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIE_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIE_CFG_MASK | LYNX_28G_PCCC_SXGMIIE_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIE_CFG(1) | LYNX_28G_PCCC_SXGMIIE_XFI,
+ .mode = "xgmii",
+ .mac = DPMAC6,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIF_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIF_CFG_MASK | LYNX_28G_PCCC_SXGMIIF_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIF_CFG(1) | LYNX_28G_PCCC_SXGMIIF_XFI,
+ .mode = "xgmii",
+ .mac = DPMAC5,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIG_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIG_CFG_MASK | LYNX_28G_PCCC_SXGMIIG_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIG_CFG(1) | LYNX_28G_PCCC_SXGMIIG_XFI,
+ .mode = "xgmii",
+ .mac = DPMAC4,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIH_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIH_CFG_MASK | LYNX_28G_PCCC_SXGMIIH_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIH_CFG(1) | LYNX_28G_PCCC_SXGMIIH_XFI,
+ .mode = "xgmii",
+ .mac = DPMAC3,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIA_CFG_MASK | LYNX_28G_PCCC_SXGMIIA_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIA_CFG(1),
++ .mode = "usxgmii",
++ .mac = DPMAC10,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIB_CFG_MASK | LYNX_28G_PCCC_SXGMIIB_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIB_CFG(1),
++ .mode = "usxgmii",
++ .mac = DPMAC9,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIC_CFG_MASK | LYNX_28G_PCCC_SXGMIIC_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIC_CFG(1),
++ .mode = "usxgmii",
++ .mac = DPMAC8,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIID_CFG_MASK | LYNX_28G_PCCC_SXGMIID_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIID_CFG(1),
++ .mode = "usxgmii",
++ .mac = DPMAC7,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIE_CFG_MASK | LYNX_28G_PCCC_SXGMIIE_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIE_CFG(1),
++ .mode = "usxgmii",
++ .mac = DPMAC6,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIF_CFG_MASK | LYNX_28G_PCCC_SXGMIIF_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIF_CFG(1),
++ .mode = "usxgmii",
++ .mac = DPMAC5,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIG_CFG_MASK | LYNX_28G_PCCC_SXGMIIG_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIG_CFG(1),
++ .mode = "usxgmii",
++ .mac = DPMAC4,
++ }, {
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIH_CFG_MASK | LYNX_28G_PCCC_SXGMIIH_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIH_CFG(1),
++ .mode = "usxgmii",
++ .mac = DPMAC3,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GA_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GA_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCD_E25GA_CFG(1),
+ .mode = "25g-aui",
+ .mac = DPMAC3,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GB_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GB_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCD_E25GB_CFG(1),
+ .mode = "25g-aui",
+ .mac = DPMAC4,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GC_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GC_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCD_E25GC_CFG(1),
+ .mode = "25g-aui",
+ .mac = DPMAC5,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GD_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GD_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCD_E25GD_CFG(1),
+ .mode = "25g-aui",
+ .mac = DPMAC6,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GE_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GE_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCD_E25GE_CFG(1),
+ .mode = "25g-aui",
+ .mac = DPMAC7,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GF_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GF_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCD_E25GF_CFG(1),
+ .mode = "25g-aui",
+ .mac = DPMAC8,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GG_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GG_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCD_E25GG_CFG(1),
+ .mode = "25g-aui",
+ .mac = DPMAC9,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GH_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCD_E25GH_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCD_E25GH_CFG(1),
+ .mode = "25g-aui",
+ .mac = DPMAC10,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
+- .pcr_ena_mask = LYNX_28G_PCCE_E40GA_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCE_E40GA_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCE_E40GA_CFG(1),
+ .mode = "xlaui4",
+ .mac = DPMAC1,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
+- .pcr_ena_mask = LYNX_28G_PCCE_E40GB_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCE_E40GB_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCE_E40GB_CFG(1),
+ .mode = "xlaui4",
+ .mac = DPMAC2,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
+- .pcr_ena_mask = LYNX_28G_PCCE_E50GA_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCE_E50GA_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCE_E50GA_CFG(1),
+ .mode = "caui2",
+ .mac = DPMAC1,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
+- .pcr_ena_mask = LYNX_28G_PCCE_E50GB_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCE_E50GB_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCE_E50GB_CFG(1),
+ .mode = "caui2",
+ .mac = DPMAC2,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
+- .pcr_ena_mask = LYNX_28G_PCCE_E100GA_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCE_E100GA_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCE_E100GA_CFG(1),
+ .mode = "caui4",
+ .mac = DPMAC1,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
+- .pcr_ena_mask = LYNX_28G_PCCE_E100GB_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCE_E100GB_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCCE_E100GB_CFG(1),
+ .mode = "caui4",
+ .mac = DPMAC2,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIA_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIA_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIA_CFG(1),
+ .mode = "sgmii",
+- .mac = DPMAC18,
++ .mac = DPMAC11,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIB_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIB_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIB_CFG(1),
+ .mode = "sgmii",
+- .mac = DPMAC17,
++ .mac = DPMAC12,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIC_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIC_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIC_CFG(1),
+ .mode = "sgmii",
+- .mac = DPMAC16,
++ .mac = DPMAC17,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIID_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIID_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIID_CFG(1),
+ .mode = "sgmii",
+- .mac = DPMAC15,
++ .mac = DPMAC18,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIE_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIE_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIE_CFG(1),
+ .mode = "sgmii",
+- .mac = DPMAC14,
++ .mac = DPMAC15,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIF_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIF_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIF_CFG(1),
+ .mode = "sgmii",
+- .mac = DPMAC13,
++ .mac = DPMAC16,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIG_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIG_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIG_CFG(1),
+ .mode = "sgmii",
+- .mac = DPMAC12,
++ .mac = DPMAC13,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
+- .pcr_ena_mask = LYNX_28G_PCC8_SGMIIH_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC8_SGMIIH_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC8_SGMIIH_CFG(1),
+ .mode = "sgmii",
+- .mac = DPMAC11,
+- }, {
+- .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIA_CFG,
+- .mode = "xgmii",
+- .mac = DPMAC18,
+- }, {
+- .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIB_CFG,
+- .mode = "xgmii",
+- .mac = DPMAC17,
+- }, {
+- .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIC_CFG,
+- .mode = "xgmii",
+- .mac = DPMAC16,
++ .mac = DPMAC14,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIID_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIG_CFG_MASK | LYNX_28G_PCCC_SXGMIIG_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIG_CFG(1) | LYNX_28G_PCCC_SXGMIIG_XFI,
+ .mode = "xgmii",
+- .mac = DPMAC15,
++ .mac = DPMAC13,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIE_CFG,
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIH_CFG_MASK | LYNX_28G_PCCC_SXGMIIH_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIH_CFG(1) | LYNX_28G_PCCC_SXGMIIH_XFI,
+ .mode = "xgmii",
+ .mac = DPMAC14,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIF_CFG,
+- .mode = "xgmii",
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIG_CFG_MASK | LYNX_28G_PCCC_SXGMIIG_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIG_CFG(1),
++ .mode = "usxgmii",
+ .mac = DPMAC13,
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIG_CFG,
+- .mode = "xgmii",
+- .mac = DPMAC12,
+- }, {
+- .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
+- .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIH_CFG,
+- .mode = "xgmii",
+- .mac = DPMAC11,
+- }, {
+- .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GA_CFG,
+- .mode = "25g-aui",
+- .mac = DPMAC18,
+- }, {
+- .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GB_CFG,
+- .mode = "25g-aui",
+- .mac = DPMAC17,
+- }, {
+- .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GC_CFG,
+- .mode = "25g-aui",
+- .mac = DPMAC16,
+- }, {
+- .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GD_CFG,
+- .mode = "25g-aui",
+- .mac = DPMAC15,
+- }, {
+- .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GE_CFG,
+- .mode = "25g-aui",
++ .pcr_ena_mask = LYNX_28G_PCCC_SXGMIIH_CFG_MASK | LYNX_28G_PCCC_SXGMIIH_XFI,
++ .pcr_ena_val = LYNX_28G_PCCC_SXGMIIH_CFG(1),
++ .mode = "usxgmii",
+ .mac = DPMAC14,
+- }, {
+- .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GF_CFG,
+- .mode = "25g-aui",
+- .mac = DPMAC13,
+- }, {
+- .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GG_CFG,
+- .mode = "25g-aui",
+- .mac = DPMAC12,
+- }, {
+- .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCD,
+- .pcr_ena_mask = LYNX_28G_PCCD_E25GH_CFG,
+- .mode = "25g-aui",
+- .mac = DPMAC11,
+ }
+ };
+
+ for (int i = 0; i < ARRAY_SIZE(ports); i++) {
+- if (*ports[i].pcr & ports[i].pcr_ena_mask) {
++ if ((*ports[i].pcr & ports[i].pcr_ena_mask) == ports[i].pcr_ena_val) {
+ macs[ports[i].mac].status = "okay";
+ macs[ports[i].mac].mode = ports[i].mode;
+ }
+@@ -448,56 +526,67 @@ static void board_fix_fdt_macs(void *fdt) {
+
+ static void board_fix_fdt_pci_sata(void *fdt) {
+ struct {
+- const u32 __iomem *pcr;
++ const u32 __iomem *const pcr;
+ const u32 pcr_ena_mask;
++ const u32 pcr_ena_val;
+ const char *const path;
+ } ports[] = {
+ {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC0,
+- .pcr_ena_mask = LYNX_28G_PCC0_PEXA_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC0_PEXA_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC0_PEXA_CFG(1),
+ .path = "/pcie at 3400000",
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC0,
+- .pcr_ena_mask = LYNX_28G_PCC0_PEXB_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC0_PEXB_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC0_PEXB_CFG(1),
+ .path = "/pcie at 3500000",
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC0,
+- .pcr_ena_mask = LYNX_28G_PCC0_PEXA_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC0_PEXA_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC0_PEXA_CFG(1),
+ .path = "/pcie at 3600000",
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC0,
+- .pcr_ena_mask = LYNX_28G_PCC0_PEXB_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC0_PEXB_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC0_PEXB_CFG(1),
+ .path = "/pcie at 3700000",
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(2) + LYNX_28G_PCC0,
+- .pcr_ena_mask = LYNX_28G_PCC0_PEXA_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC0_PEXA_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC0_PEXA_CFG(1),
+ .path = "/pcie at 3800000",
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(2) + LYNX_28G_PCC0,
+- .pcr_ena_mask = LYNX_28G_PCC0_PEXB_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC0_PEXB_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC0_PEXB_CFG(1),
+ .path = "/pcie at 3900000",
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC2,
+- .pcr_ena_mask = LYNX_28G_PCC2_SATAA_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC2_SATAA_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC2_SATAA_CFG(1),
+ .path = "/sata at 3200000",
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC2,
+- .pcr_ena_mask = LYNX_28G_PCC2_SATAB_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC2_SATAB_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC2_SATAB_CFG(1),
+ .path = "/sata at 3210000",
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC2,
+- .pcr_ena_mask = LYNX_28G_PCC2_SATAC_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC2_SATAC_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC2_SATAC_CFG(1),
+ .path = "/sata at 3220000",
+ }, {
+ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC2,
+- .pcr_ena_mask = LYNX_28G_PCC2_SATAD_CFG,
++ .pcr_ena_mask = LYNX_28G_PCC2_SATAD_CFG_MASK,
++ .pcr_ena_val = LYNX_28G_PCC2_SATAD_CFG(1),
+ .path = "/sata at 3230000",
+ },
+ };
+
+ for (int i = 0; i < ARRAY_SIZE(ports); i++) {
+ const char *status = "disabled";
+- if (*ports[i].pcr & ports[i].pcr_ena_mask)
++ if ((*ports[i].pcr & ports[i].pcr_ena_mask) == ports[i].pcr_ena_val)
+ status = "okay";
+
+ do_fixup_by_path_string(fdt, ports[i].path, "status", status);
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0025-board-solidrun-lx2160acex7-disable-disabled-ports-pr.patch b/board/solidrun/lx2160acex7/patches/uboot/0025-board-solidrun-lx2160acex7-disable-disabled-ports-pr.patch
new file mode 100644
index 0000000000..feda052455
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0025-board-solidrun-lx2160acex7-disable-disabled-ports-pr.patch
@@ -0,0 +1,367 @@
+From 7e08716c520590240497c3beedb1a34f0603af3b Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Wed, 27 Aug 2025 17:06:19 +0200
+Subject: [PATCH 25/25] board: solidrun: lx2160acex7: disable disabled ports
+ protocol converters
+
+LX2160A can disable ports through DEVDISR registers, which cuts their
+root clocks. This does not disable the protocol converters connected to
+the MACs.
+
+Evaluate DEVDISR2 register to disable the protocol converters for
+disabled MACs.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ board/solidrun/lx2160acex7/lx2160a.c | 5 +
+ board/solidrun/lx2160acex7/serdes.c | 304 +++++++++++++++++++++++++++
+ 2 files changed, 309 insertions(+)
+
+diff --git a/board/solidrun/lx2160acex7/lx2160a.c b/board/solidrun/lx2160acex7/lx2160a.c
+index dbfb1dc9d4d..6e12f868759 100644
+--- a/board/solidrun/lx2160acex7/lx2160a.c
++++ b/board/solidrun/lx2160acex7/lx2160a.c
+@@ -22,6 +22,8 @@
+
+ DECLARE_GLOBAL_DATA_PTR;
+
++void board_disable_unused_proto_converters(void);
++
+ int board_early_init_f(void)
+ {
+ fsl_lsch3_early_init_f();
+@@ -33,6 +35,9 @@ int board_early_init_f(void)
+ */
+ memcpy((void *)0x700100100, (void *)0x01e00100, 0x180);
+
++ /* disable unused protocol converters on disabled ports */
++ board_disable_unused_proto_converters();
++
+ return 0;
+ }
+
+diff --git a/board/solidrun/lx2160acex7/serdes.c b/board/solidrun/lx2160acex7/serdes.c
+index 8e19a471b04..b4bc78c5d2c 100644
+--- a/board/solidrun/lx2160acex7/serdes.c
++++ b/board/solidrun/lx2160acex7/serdes.c
+@@ -9,6 +9,40 @@
+ /* Devoce Configuration Register base address */
+ #define DCFG_CCSR_BASE (void *)0x01E00000
+
++/* Device Disable Register 1 */
++#define DCFG_CCSR_DEVDISR1 0x0070
++#define DCFG_CCSR_DEVDISR1_DCE BIT(25)
++#define DCFG_CCSR_DEVDISR1_SEC BIT(22)
++#define DCFG_CCSR_DEVDISR1_SATA4 BIT(19)
++#define DCFG_CCSR_DEVDISR1_SATA3 BIT(18)
++#define DCFG_CCSR_DEVDISR1_SATA2 BIT(17)
++#define DCFG_CCSR_DEVDISR1_SATA1 BIT(16)
++#define DCFG_CCSR_DEVDISR1_USB1 BIT(12)
++#define DCFG_CCSR_DEVDISR1_ESDHC2 BIT(10)
++#define DCFG_CCSR_DEVDISR1_QDMA BIT(8)
++#define DCFG_CCSR_DEVDISR1_ESDHC1 BIT(2)
++
++/* Device Disable Register 2 */
++#define DCFG_CCSR_DEVDISR2 0x0074
++#define DCFG_CCSR_DEVDISR2_MAC18 BIT(17)
++#define DCFG_CCSR_DEVDISR2_MAC17 BIT(16)
++#define DCFG_CCSR_DEVDISR2_MAC16 BIT(15)
++#define DCFG_CCSR_DEVDISR2_MAC15 BIT(14)
++#define DCFG_CCSR_DEVDISR2_MAC14 BIT(13)
++#define DCFG_CCSR_DEVDISR2_MAC13 BIT(12)
++#define DCFG_CCSR_DEVDISR2_MAC12 BIT(11)
++#define DCFG_CCSR_DEVDISR2_MAC11 BIT(10)
++#define DCFG_CCSR_DEVDISR2_MAC10 BIT(9)
++#define DCFG_CCSR_DEVDISR2_MAC9 BIT(8)
++#define DCFG_CCSR_DEVDISR2_MAC8 BIT(7)
++#define DCFG_CCSR_DEVDISR2_MAC7 BIT(6)
++#define DCFG_CCSR_DEVDISR2_MAC6 BIT(5)
++#define DCFG_CCSR_DEVDISR2_MAC5 BIT(4)
++#define DCFG_CCSR_DEVDISR2_MAC4 BIT(3)
++#define DCFG_CCSR_DEVDISR2_MAC3 BIT(2)
++#define DCFG_CCSR_DEVDISR2_MAC2 BIT(1)
++#define DCFG_CCSR_DEVDISR2_MAC1 BIT(0)
++
+ /* SerDes base address */
+ #define LYNX_28G_SDn_BASE(block) (DCFG_CCSR_BASE + 0x000A0000 + (block) * 0x10000)
+
+@@ -158,6 +192,276 @@ enum {
+ DPMAC_MAX
+ };
+
++/* Device Disable Register 1 */
++#define DCFG_CCSR_DEVDISR1 0x0070
++#define DCFG_CCSR_DEVDISR1_DCE BIT(25)
++#define DCFG_CCSR_DEVDISR1_SEC BIT(22)
++#define DCFG_CCSR_DEVDISR1_SATA4 BIT(19)
++#define DCFG_CCSR_DEVDISR1_SATA3 BIT(18)
++#define DCFG_CCSR_DEVDISR1_SATA2 BIT(17)
++#define DCFG_CCSR_DEVDISR1_SATA1 BIT(16)
++#define DCFG_CCSR_DEVDISR1_USB1 BIT(12)
++#define DCFG_CCSR_DEVDISR1_ESDHC2 BIT(10)
++#define DCFG_CCSR_DEVDISR1_QDMA BIT(8)
++#define DCFG_CCSR_DEVDISR1_ESDHC1 BIT(2)
++
++/* Device Disable Register 2 */
++#define DCFG_CCSR_DEVDISR2 0x0074
++#define DCFG_CCSR_DEVDISR2_MAC18 BIT(17)
++#define DCFG_CCSR_DEVDISR2_MAC17 BIT(16)
++#define DCFG_CCSR_DEVDISR2_MAC16 BIT(15)
++#define DCFG_CCSR_DEVDISR2_MAC15 BIT(14)
++#define DCFG_CCSR_DEVDISR2_MAC14 BIT(13)
++#define DCFG_CCSR_DEVDISR2_MAC13 BIT(12)
++#define DCFG_CCSR_DEVDISR2_MAC12 BIT(11)
++#define DCFG_CCSR_DEVDISR2_MAC11 BIT(10)
++#define DCFG_CCSR_DEVDISR2_MAC10 BIT(9)
++#define DCFG_CCSR_DEVDISR2_MAC9 BIT(8)
++#define DCFG_CCSR_DEVDISR2_MAC8 BIT(7)
++#define DCFG_CCSR_DEVDISR2_MAC7 BIT(6)
++#define DCFG_CCSR_DEVDISR2_MAC6 BIT(5)
++#define DCFG_CCSR_DEVDISR2_MAC5 BIT(4)
++#define DCFG_CCSR_DEVDISR2_MAC4 BIT(3)
++#define DCFG_CCSR_DEVDISR2_MAC3 BIT(2)
++#define DCFG_CCSR_DEVDISR2_MAC2 BIT(1)
++#define DCFG_CCSR_DEVDISR2_MAC1 BIT(0)
++
++/*
++ * evaluate DEVDISR registers to understand which interfaces are not
++ * available, and disable their protocol converters.
++ */
++void board_disable_unused_proto_converters(void) {
++ struct {
++ const u32 __iomem *devdisr;
++ const u32 devdisr_bit;
++ u32 __iomem *const pcr;
++ const u32 pcr_dis_mask;
++ const u32 pcr_dis_val;
++ } map[] = {
++ { /* dpmac1: 40G/50G/100G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC1,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
++ .pcr_dis_mask = LYNX_28G_PCCE_E40GA_CFG_MASK | LYNX_28G_PCCE_E50GA_CFG_MASK | LYNX_28G_PCCE_E100GA_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCE_E40GA_CFG(0) | LYNX_28G_PCCE_E50GA_CFG(0) | LYNX_28G_PCCE_E100GA_CFG(0),
++ }, { /* dpmac2: 40G/50G/100G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC2,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCE,
++ .pcr_dis_mask = LYNX_28G_PCCE_E40GB_CFG_MASK | LYNX_28G_PCCE_E50GB_CFG_MASK | LYNX_28G_PCCE_E100GB_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCE_E40GB_CFG(0) | LYNX_28G_PCCE_E50GB_CFG(0) | LYNX_28G_PCCE_E100GB_CFG(0),
++ }, { /* dpmac3: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC3,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIH_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIH_CFG(0),
++ }, { /* dpmac3: 10G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC3,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_dis_mask = LYNX_28G_PCCC_SXGMIIH_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCC_SXGMIIH_CFG(0),
++ }, { /* dpmac3: 25G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC3,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_dis_mask = LYNX_28G_PCCD_E25GA_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCD_E25GA_CFG(0),
++ }, { /* dpmac4: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC4,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIG_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIG_CFG(0),
++ }, { /* dpmac4: 10G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC4,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_dis_mask = LYNX_28G_PCCC_SXGMIIG_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCC_SXGMIIG_CFG(0),
++ }, { /* dpmac4: 25G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC4,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_dis_mask = LYNX_28G_PCCD_E25GB_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCD_E25GB_CFG(0),
++ }, { /* dpmac5: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC5,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIF_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIF_CFG(0),
++ }, { /* dpmac5: 10G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC5,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_dis_mask = LYNX_28G_PCCC_SXGMIIF_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCC_SXGMIIF_CFG(0),
++ }, { /* dpmac5: 25G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC5,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_dis_mask = LYNX_28G_PCCD_E25GC_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCD_E25GC_CFG(0),
++ }, { /* dpmac6: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC6,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIE_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIE_CFG(0),
++ }, { /* dpmac6: 10G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC6,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_dis_mask = LYNX_28G_PCCC_SXGMIIE_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCC_SXGMIIE_CFG(0),
++ }, { /* dpmac6: 25G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC6,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_dis_mask = LYNX_28G_PCCD_E25GD_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCD_E25GD_CFG(0),
++ }, { /* dpmac7: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC7,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIID_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIID_CFG(0),
++ }, { /* dpmac7: 10G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC7,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_dis_mask = LYNX_28G_PCCC_SXGMIID_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCC_SXGMIID_CFG(0),
++ }, { /* dpmac7: 25G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC7,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_dis_mask = LYNX_28G_PCCD_E25GE_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCD_E25GE_CFG(0),
++ }, { /* dpmac8: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC8,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIC_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIC_CFG(0),
++ }, { /* dpmac8: 10G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC8,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_dis_mask = LYNX_28G_PCCC_SXGMIIC_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCC_SXGMIIC_CFG(0),
++ }, { /* dpmac8: 25G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC8,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_dis_mask = LYNX_28G_PCCD_E25GF_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCD_E25GF_CFG(0),
++ }, { /* dpmac9: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC9,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIB_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIB_CFG(0),
++ }, { /* dpmac9: 10G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC9,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_dis_mask = LYNX_28G_PCCC_SXGMIIB_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCC_SXGMIIB_CFG(0),
++ }, { /* dpmac9: 25G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC9,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_dis_mask = LYNX_28G_PCCD_E25GG_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCD_E25GG_CFG(0),
++ }, { /* dpmac10: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC10,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIA_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIA_CFG(0),
++ }, { /* dpmac10: 10G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC10,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCC,
++ .pcr_dis_mask = LYNX_28G_PCCC_SXGMIIA_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCC_SXGMIIA_CFG(0),
++ }, { /* dpmac10: 25G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC10,
++ .pcr = LYNX_28G_SDn_BASE(0) + LYNX_28G_PCCD,
++ .pcr_dis_mask = LYNX_28G_PCCD_E25GH_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCD_E25GH_CFG(0),
++ }, { /* dpmac11: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC11,
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIA_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIA_CFG(0),
++ }, { /* dpmac12: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC12,
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIB_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIB_CFG(0),
++ }, { /* dpmac17: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC17,
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIC_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIC_CFG(0),
++ }, { /* dpmac18: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC18,
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIID_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIID_CFG(0),
++ }, { /* dpmac15: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC15,
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIE_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIE_CFG(0),
++ }, { /* dpmac16: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC16,
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIF_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIF_CFG(0),
++ }, { /* dpmac13: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC13,
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIG_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIG_CFG(0),
++ }, { /* dpmac13: 10G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC13,
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
++ .pcr_dis_mask = LYNX_28G_PCCC_SXGMIIG_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCC_SXGMIIG_CFG(0),
++ }, { /* dpmac14: 1G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC14,
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCC8,
++ .pcr_dis_mask = LYNX_28G_PCC8_SGMIIH_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCC8_SGMIIH_CFG(0),
++ }, { /* dpmac14: 10G */
++ .devdisr = DCFG_CCSR_BASE + DCFG_CCSR_DEVDISR2,
++ .devdisr_bit = DCFG_CCSR_DEVDISR2_MAC14,
++ .pcr = LYNX_28G_SDn_BASE(1) + LYNX_28G_PCCC,
++ .pcr_dis_mask = LYNX_28G_PCCC_SXGMIIH_CFG_MASK,
++ .pcr_dis_val = LYNX_28G_PCCC_SXGMIIH_CFG(0),
++ },
++ };
++
++ for (int i = 0; i < ARRAY_SIZE(map); i++)
++ if (*map[i].devdisr & map[i].devdisr_bit)
++ *map[i].pcr &= ~map[i].pcr_dis_mask | map[i].pcr_dis_val;
++}
++
+ #ifdef CONFIG_OF_BOARD_FIXUP
+
+ /* fix mac nodes based on serdes protocol */
+--
+2.43.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0026-cmd-add-ds250dfx10-control.patch b/board/solidrun/lx2160acex7/patches/uboot/0026-cmd-add-ds250dfx10-control.patch
new file mode 100644
index 0000000000..3d7a042fe0
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0026-cmd-add-ds250dfx10-control.patch
@@ -0,0 +1,994 @@
+From b8fe1057d42e4c7b4d02851c6d0125e9471114cb Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Sun, 31 Aug 2025 18:13:59 +0200
+Subject: [PATCH] cmd: add ds250dfx10 control
+
+Notably DS250DFx10 can generate prbs patterns, count errors and create
+eye diagram - all are useful for testing equalization parameters.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ cmd/Kconfig | 5 +
+ cmd/Makefile | 2 +
+ cmd/ds250dfx10.c | 927 ++++++++++++++++++++++++++++++
+ configs/lx2160acex7_tfa_defconfig | 1 +
+ 4 files changed, 935 insertions(+)
+ create mode 100644 cmd/ds250dfx10.c
+
+diff --git a/cmd/Kconfig b/cmd/Kconfig
+index 413051ac4a1..de938f24184 100644
+--- a/cmd/Kconfig
++++ b/cmd/Kconfig
+@@ -2898,6 +2898,11 @@ config CMD_STACKPROTECTOR_TEST
+ The stackprot_test command will force a stack overrun to test
+ the stack smashing detection mechanisms.
+
++config CMD_DS250DFX10
++ bool "DS250FDx10 retimer device control"
++ help
++ Enable ds250dfx10 command to control DS250DFx10 retimer device.
++
+ endmenu
+
+ config CMD_UBI
+diff --git a/cmd/Makefile b/cmd/Makefile
+index 87133cc27a8..696ae277a47 100644
+--- a/cmd/Makefile
++++ b/cmd/Makefile
+@@ -246,6 +246,8 @@ obj-$(CONFIG_ARCH_MVEBU) += mvebu/
+ obj-$(CONFIG_ARCH_KEYSTONE) += ti/
+ obj-$(CONFIG_ARCH_K3) += ti/
+ obj-$(CONFIG_ARCH_OMAP2PLUS) += ti/
++
++obj-$(CONFIG_CMD_DS250DFX10) += ds250dfx10.o
+ endif # !CONFIG_SPL_BUILD
+
+ obj-$(CONFIG_$(SPL_)CMD_TLV_EEPROM) += tlv_eeprom.o
+diff --git a/cmd/ds250dfx10.c b/cmd/ds250dfx10.c
+new file mode 100644
+index 00000000000..4977b56e66b
+--- /dev/null
++++ b/cmd/ds250dfx10.c
+@@ -0,0 +1,927 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2025 Josua Mayer <josua at solid-run.com>
++ */
++
++#include <command.h>
++#include <dm/device.h>
++#include <dm/uclass.h>
++#include <i2c.h>
++
++/* DS250DFx10 Shared Registers reg offset length */
++
++/* DS250DFx10 Channel Registers reg offset length */
++#define DS250DFX10_REG_POL_INV_DET 0x01, 6, 1
++#define DS250DFX10_REG_PRBS_SEQ_DET 0x01, 1, 4
++#define DS250DFX10_REG_BYPASS_PFD_OV 0x09, 5, 1
++#define DS250DFX10_REG_DES_PD 0x0D, 7, 1
++#define DS250DFX10_EOM_PD 0x11, 5, 1
++#define DS250DFX10_EOM_SEL_VRANGE 0x11, 6, 2
++#define DS250DFX10_SER_EN 0x1E, 4, 1
++#define DS250DFX10_PFD_SEL_DATA_PRELCK 0x1E, 5, 3
++#define DS250DFX10_EOM_START 0x24, 0, 1
++#define DS250DFX10_FAST_EOM 0x24, 7, 1
++#define DS250DFX10_EOM_DATA_HI 0x25, 0, 8
++#define DS250DFX10_EOM_DATA_LO 0x26, 0, 8
++#define DS250DFX10_VEO_SCALE 0x2C, 6, 1
++#define DS250DFX10_PRBS_PATTERN_SEL_HI 0x2E, 2, 1
++#define DS250DFX10_PRBS_PATTERN_SEL_LO 0x30, 0, 2
++#define DS250DFX10_PRBS_EN_DIG_CLK 0x30, 3, 1
++#define DS250DFX10_RELOAD_PRBS_CHKR 0x30, 4, 1
++#define DS250DFX10_HV_LOCKMON_EN 0x67, 5, 1
++#define DS250DFX10_CDR_LOCK_STATUS 0x78, 4, 1
++#define DS250DFX10_PRBS_GEN_EN 0x79, 5, 1
++#define DS250DFX10_PRBS_CHKR_EN 0x79, 6, 1
++#define DS250DFX10_RST_PRBS_CNTS 0x82, 6, 1
++#define DS250DFX10_FREEZE_PRBS_CNTR 0x82, 7, 1
++#define DS250DFX10_PRBS_ERR_CNT_HI 0x83, 0, 3
++#define DS250DFX10_PRBS_ERR_CNT_LO 0x84, 0, 8
++
++/* DS250DFx10 Global Registers reg offset length */
++#define DS250DFX10_CHAN_CONFIG_ID 0xEF, 0, 4
++#define DS250DFX10_DEVICE_ID 0xF1, 0, 8
++#define DS250DFX10_EN_CH(n) 0xFC, n, 1
++#define DS250DFX10_VENDOR_ID 0xFE, 0, 8
++#define DS250DFX10_EN_SHARE_Q0 0xFF, 4, 1
++#define DS250DFX10_EN_SHARE_Q1 0xFF, 5, 1
++#define DS250DFX10_EN_CH_SMB 0xFF, 0, 1
++
++enum ds250dfx10_type {
++ DS250DF410 = 0,
++ DS250DF810,
++ DS250DFX10_TYPE_MAX,
++};
++
++static const char *const ds250dfx10_type_str[DS250DFX10_TYPE_MAX] = {
++ "DS250DF410",
++ "DS250DF810",
++};
++
++enum ds250dfx10_eom_vrange {
++ DS250DFX10_EOM_100MV = 0,
++ DS250DFX10_EOM_200MV,
++ DS250DFX10_EOM_300MV,
++ DS250DFX10_EOM_400MV,
++ DS250DFX10_EOM_VRANGE_MAX,
++};
++
++static const char *const ds250dfx10_eom_vrange_str[DS250DFX10_EOM_VRANGE_MAX] = {
++ "+-100mV",
++ "+-200mV",
++ "+-300mV",
++ "+-400mV",
++};
++
++enum ds250dfx10_prbs_pattern {
++ DS250DFX10_PRBS7 = 0,
++ DS250DFX10_PRBS9,
++ DS250DFX10_PRBS11,
++ DS250DFX10_PRBS15,
++ DS250DFX10_PRBS23,
++ DS250DFX10_PRBS31,
++ DS250DFX10_PRBS58,
++ DS250DFX10_PRBS63,
++ DS250DFX10_PRBS_PATTERN_MAX,
++};
++
++static const char *const ds250dfx10_prbs_pattern_str[DS250DFX10_PRBS_PATTERN_MAX] = {
++ "PRBS7",
++ "PRBS9",
++ "PRBS11",
++ "PRBS15",
++ "PRBS23",
++ "PRBS31",
++ "PRBS58",
++ "PRBS63",
++};
++
++static enum ds250dfx10_prbs_pattern ds250dfx10_prbs_pattern_parse(const char *const str)
++{
++ for (int i = 0; i < DS250DFX10_PRBS_PATTERN_MAX; i++) {
++ if (!strcmp(str, ds250dfx10_prbs_pattern_str[i]))
++ return i;
++ }
++
++ return DS250DFX10_PRBS_PATTERN_MAX;
++}
++
++static uint8_t ds250dfx10_channel_count[DS250DFX10_TYPE_MAX] = {
++ 4,
++ 8,
++};
++
++enum ds250dfx10_eom_fmt {
++ DS250DFX10_CSV,
++ DS250DFX10_VTE,
++ DS250DFX10_EOM_FMT_MAX,
++};
++
++static const char *const ds250dfx10_eom_fmt_str[DS250DFX10_EOM_FMT_MAX] = {
++ "CSV",
++ "VTE",
++};
++
++static enum ds250dfx10_eom_fmt ds250dfx10_eom_fmt_parse(const char *const str)
++{
++ for (int i = 0; i < DS250DFX10_EOM_FMT_MAX; i++) {
++ if (!strcmp(str, ds250dfx10_eom_fmt_str[i]))
++ return i;
++ }
++
++ return DS250DFX10_EOM_FMT_MAX;
++}
++
++/* internal state */
++static struct _ds250dfx10_priv {
++ struct udevice *dev;
++ enum ds250dfx10_type type;
++} _priv;
++static struct _ds250dfx10_priv *const priv = &_priv;
++
++inline int ds250dfx10_read(uint8_t reg, uint8_t, uint8_t, uint8_t *const buffer, const uint8_t len)
++{
++ return dm_i2c_read(priv->dev, reg, buffer, len);
++}
++
++static int ds250dfx10_get(const uint8_t reg, const uint8_t offset, const uint8_t len, uint8_t *const val)
++{
++ int ret;
++ const uint8_t mask = ((2 << (len - 1)) - 1) << offset;
++ uint8_t _val = 0;
++
++ ret = dm_i2c_read(priv->dev, reg, &_val, sizeof(_val));
++ if (ret) {
++ printf("failed to read register %#04x: %d\n", reg, ret);
++ return ret;
++ }
++ //printf("dm_i2c_read %#04x: %#04x\n", reg, _val);
++
++ *val = (_val & mask) >> offset;
++
++ return 0;
++}
++
++static int ds250dfx10_set(const uint8_t reg, const uint8_t offset, const uint8_t len, const uint8_t val)
++{
++ int ret;
++ const uint8_t mask = ((2 << (len - 1)) - 1) << offset;
++ uint8_t _val = 0;
++
++ ret = dm_i2c_read(priv->dev, reg, &_val, sizeof(_val));
++ if (ret) {
++ printf("failed to read register %#04x: %d\n", reg, ret);
++ return ret;
++ }
++
++ _val &= ~mask;
++ _val |= (val << offset) & mask;
++
++ dm_i2c_write(priv->dev, reg, &_val, sizeof(_val));
++ if (ret)
++ printf("failed to write register %#04x = %#04x: %d\n", reg, _val, ret);
++ //printf("dm_i2c_write %#04x = %#04x\n", reg, _val);
++
++ return ret;
++}
++
++static int do_ds250dfx10_dev(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
++{
++ const char * _bus;
++ struct udevice *bus;
++ unsigned long _addr;
++ unsigned int addr;
++ uint8_t vendor_id, device_id, chan_conf;
++ int ret;
++
++ switch (argc) {
++ case 3:
++ _bus = argv[1];
++ ret = uclass_get_device_by_name(UCLASS_I2C, _bus, &bus);
++ if (ret) {
++ printf("failed to get i2c bus %s: %d\n", _bus, ret);
++ return CMD_RET_FAILURE;
++ }
++
++ _addr = hextoul(argv[2], NULL);
++ if (_addr > UINT_MAX) {
++ printf("i2c bus address invalid: %ld\n", _addr);
++ return CMD_RET_FAILURE;
++ }
++ addr = _addr;
++
++ ret = i2c_get_chip(bus, addr, 1, &priv->dev);
++ if (ret) {
++ printf("failed to get %s->retimer@%x: %d\n", _bus, addr, ret);
++ return CMD_RET_FAILURE;
++ }
++
++ /* read vendor id */
++ ret = ds250dfx10_get(DS250DFX10_VENDOR_ID, &vendor_id);
++ if (ret < 0) {
++ priv->dev = NULL;
++ return CMD_RET_FAILURE;
++ }
++
++ /* read device id */
++ ret = ds250dfx10_get(DS250DFX10_DEVICE_ID, &device_id);
++ if (ret < 0) {
++ priv->dev = NULL;
++ return CMD_RET_FAILURE;
++ }
++
++ /* read channel config */
++ ret = ds250dfx10_get(DS250DFX10_CHAN_CONFIG_ID, &chan_conf);
++ if (ret < 0) {
++ priv->dev = NULL;
++ return CMD_RET_FAILURE;
++ }
++
++ if ((vendor_id == 0x03) && (device_id == 0x10) && (chan_conf == 0x0C)) {
++ priv->type = DS250DF810;
++ } else if ((vendor_id = 0x03) && (device_id == 0x10) && (chan_conf == 0x0E)) {
++ priv->type = DS250DF410;
++ } else {
++ printf("unknown device id=%#04x, chan_conf=%#04x\n", device_id, chan_conf);
++ priv->dev = NULL;
++ return CMD_RET_FAILURE;
++ }
++
++ if (!priv->dev) {
++ puts("no retimer selected\n");
++ return CMD_RET_FAILURE;
++ }
++
++ printf("selected %s on %s at %#04x\n", ds250dfx10_type_str[priv->type], _bus, addr);
++ return CMD_RET_SUCCESS;
++ default:
++ return CMD_RET_USAGE;
++ }
++}
++
++static int do_ds250dfx10_chan_get(void)
++{
++ int ret;
++ uint8_t val;
++ uint8_t channels = 0;
++
++ for (int i = 0; i < ds250dfx10_channel_count[priv->type]; i++) {
++ ret = ds250dfx10_get(DS250DFX10_EN_CH(i), &val);
++ if (ret)
++ return ret;
++
++ if (val)
++ channels |= (1 << i);
++ }
++
++ return channels;
++}
++
++static int do_ds250dfx10_chan_set(uint8_t channels)
++{
++ int ret = 0;
++
++ for (int i = 0; i < ds250dfx10_channel_count[priv->type]; i++) {
++ ret = ds250dfx10_set(DS250DFX10_EN_CH(i), !!(channels & (1 << i)));
++ if (ret)
++ return ret;
++ }
++
++ return ret;
++}
++
++static int do_ds250dfx10_chan(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
++{
++ int ret;
++ uint8_t channels;
++ unsigned long channel;
++
++ if (!priv->dev) {
++ puts("no device selected\n");
++ return CMD_RET_FAILURE;
++ }
++
++ switch (argc) {
++ case 2:
++ channel = simple_strtoul(argv[1], NULL, 0);
++ if (channel < 0 || channel >= ds250dfx10_channel_count[priv->type]) {
++ printf("invalid channel: %ld\n", channel);
++ return CMD_RET_FAILURE;
++ }
++
++ ret = do_ds250dfx10_chan_set((1 << channel));
++ if (ret)
++ return CMD_RET_FAILURE;
++
++ fallthrough;
++ case 1:
++ ret = do_ds250dfx10_chan_get();
++ if (ret < 0)
++ return CMD_RET_FAILURE;
++ channels = ret;
++
++ puts("selected channel:");
++ for (int i = 0; i < ds250dfx10_channel_count[priv->type]; i++) {
++ if (channels & (1 << i)) {
++ putc(' ');
++ putc('0' + i);
++ }
++ }
++
++ if (!channels)
++ puts(" none");
++
++ putc('\n');
++
++ return CMD_RET_SUCCESS;
++ default:
++ return CMD_RET_USAGE;
++ }
++}
++
++static int do_ds250dfx10_pttgen_stop(void)
++{
++ int ret;
++ uint8_t val;
++
++ /* enable access to channel registers */
++ ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 1);
++ if (ret)
++ goto do_ds250dfx10_pttgen_stop_ret;
++
++ /* confirm generator is active */
++ ret = ds250dfx10_get(DS250DFX10_PRBS_GEN_EN, &val);
++ if (ret) {
++ goto do_ds250dfx10_pttgen_stop_cleanup;
++ } else if (!val) {
++ puts("prbs generator not active\n");
++ ret = -EINVAL;
++ goto do_ds250dfx10_pttgen_stop_cleanup;
++ }
++
++ /* disable output override */
++ ret = ds250dfx10_set(DS250DFX10_REG_BYPASS_PFD_OV, 0);
++ if (ret)
++ goto do_ds250dfx10_pttgen_stop_cleanup;
++
++ /* disable prbs generator */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_GEN_EN, 0);
++ if (ret)
++ goto do_ds250dfx10_pttgen_stop_cleanup;
++
++ /* disable prbs clock */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_EN_DIG_CLK, 0);
++ if (ret)
++ goto do_ds250dfx10_pttgen_stop_cleanup;
++
++ /* disable serializer */
++ ret = ds250dfx10_set(DS250DFX10_SER_EN, 0);
++ if (ret)
++ goto do_ds250dfx10_pttgen_stop_cleanup;
++
++ puts("prbs generator stopped\n");
++
++do_ds250dfx10_pttgen_stop_cleanup:
++ /* disable access to channel registers */
++ ds250dfx10_set(DS250DFX10_EN_CH_SMB, 0);
++
++do_ds250dfx10_pttgen_stop_ret:
++ return ret;
++}
++
++static int do_ds250dfx10_pttgen_start(const enum ds250dfx10_prbs_pattern prbs_ptt)
++{
++ int ret;
++ const union {
++ struct {
++ uint8_t lo : 2;
++ uint8_t hi : 1;
++ } bits;
++ enum ds250dfx10_prbs_pattern sel;
++ } prbs_ptt_sel = { .sel = prbs_ptt };
++
++ /* enable access to channel registers */
++ ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 1);
++ if (ret)
++ goto do_ds250dfx10_pttgen_start_ret;
++
++ /* select pattern */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_PATTERN_SEL_HI, prbs_ptt_sel.bits.hi);
++ if (ret)
++ goto do_ds250dfx10_pttgen_start_cleanup;
++
++ ret = ds250dfx10_set(DS250DFX10_PRBS_PATTERN_SEL_LO, prbs_ptt_sel.bits.lo);
++ if (ret)
++ goto do_ds250dfx10_pttgen_start_cleanup;
++
++ /* enable serializer */
++ ret = ds250dfx10_set(DS250DFX10_SER_EN, 1);
++ if (ret)
++ goto do_ds250dfx10_pttgen_start_cleanup;
++
++ /* disable prbs generator (to reset if active) */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_GEN_EN, 0);
++ if (ret)
++ goto do_ds250dfx10_pttgen_start_cleanup;
++
++ /* enable prbs generator */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_GEN_EN, 1);
++ if (ret)
++ goto do_ds250dfx10_pttgen_start_cleanup;
++
++ /* disable prbs clock (to reset if active) */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_EN_DIG_CLK, 0);
++ if (ret)
++ goto do_ds250dfx10_pttgen_start_cleanup;
++
++ /* enable prbs clock */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_EN_DIG_CLK, 1);
++ if (ret)
++ goto do_ds250dfx10_pttgen_start_cleanup;
++
++ /* enable prbs generator output */
++ ret = ds250dfx10_set(DS250DFX10_PFD_SEL_DATA_PRELCK, 4);
++ if (ret)
++ goto do_ds250dfx10_pttgen_start_cleanup;
++
++ /* enable output override */
++ ret = ds250dfx10_set(DS250DFX10_REG_BYPASS_PFD_OV, 1);
++ if (ret)
++ goto do_ds250dfx10_pttgen_start_cleanup;
++
++ printf("PRBS generator started with %s\n", ds250dfx10_prbs_pattern_str[prbs_ptt]);
++
++do_ds250dfx10_pttgen_start_cleanup:
++ /* disable access to channel registers */
++ ds250dfx10_set(DS250DFX10_EN_CH_SMB, 0);
++
++do_ds250dfx10_pttgen_start_ret:
++ return ret;
++}
++
++static int do_ds250dfx10_pttgen(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
++{
++ int ret;
++
++ enum ds250dfx10_prbs_pattern prbs_ptt;
++
++ if (!priv->dev) {
++ puts("no device selected\n");
++ return CMD_RET_FAILURE;
++ }
++
++ ret = do_ds250dfx10_chan_get();
++ if (ret < 0) {
++ return CMD_RET_FAILURE;
++ } else if (ret == 0) {
++ puts("no channel selected\n");
++ return CMD_RET_FAILURE;
++ }
++
++ if (argc != 2)
++ return CMD_RET_USAGE;
++
++ if (!strcmp(argv[1], "stop")) {
++ ret = do_ds250dfx10_pttgen_stop();
++ if (ret)
++ return CMD_RET_FAILURE;
++
++ return CMD_RET_SUCCESS;
++ }
++
++ ret = ds250dfx10_prbs_pattern_parse(argv[1]);
++ if (ret == DS250DFX10_PRBS_PATTERN_MAX) {
++ printf("unknown pattern \"%s\"\n", argv[1]);
++ return CMD_RET_FAILURE;
++ }
++ prbs_ptt = ret;
++
++ ret = do_ds250dfx10_pttgen_start(prbs_ptt);
++ if (ret)
++ return CMD_RET_FAILURE;
++
++ return CMD_RET_SUCCESS;
++}
++
++static int do_ds250dfx10_pttchk_show(void)
++{
++ int ret;
++ uint8_t val1;
++ uint16_t val2;
++ enum ds250dfx10_prbs_pattern prbs_ptt;
++
++ /* enable access to channel registers */
++ ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 1);
++ if (ret)
++ goto do_ds250dfx10_pttchk_show_ret;
++
++ /* read detected pattern */
++ ret = ds250dfx10_get(DS250DFX10_REG_PRBS_SEQ_DET, &val1);
++ if (ret) {
++ goto do_ds250dfx10_pttchk_show_cleanup;
++ } else if (!(val1 & 0x08)) {
++ printf("no pattern detected\n");
++ goto do_ds250dfx10_pttchk_show_cleanup;
++ }
++ prbs_ptt = val1 & 0x07;
++
++ /* read polarity */
++ ret = ds250dfx10_get(DS250DFX10_REG_POL_INV_DET, &val1);
++ if (ret)
++ goto do_ds250dfx10_pttchk_show_cleanup;
++
++ puts("detected ");
++ puts(ds250dfx10_prbs_pattern_str[prbs_ptt]);
++ if (val1)
++ puts(", polarity inverted");
++ putc('\n');
++
++ /* freeze error counter */
++ ret = ds250dfx10_set(DS250DFX10_FREEZE_PRBS_CNTR, 1);
++ if (ret)
++ goto do_ds250dfx10_pttchk_show_cleanup;
++
++ /* read error counter */
++ ret = ds250dfx10_read(DS250DFX10_PRBS_ERR_CNT_HI, (uint8_t *)&val2, sizeof(val2));
++ if (ret)
++ goto do_ds250dfx10_pttchk_show_cleanup;
++ val2 &= 0x07FF;
++
++ /* release error counter */
++ ret = ds250dfx10_set(DS250DFX10_FREEZE_PRBS_CNTR, 0);
++ if (ret)
++ goto do_ds250dfx10_pttchk_show_cleanup;
++
++ printf("errors: %u\n", val2);
++
++do_ds250dfx10_pttchk_show_cleanup:
++ /* disable access to channel registers */
++ ds250dfx10_set(DS250DFX10_EN_CH_SMB, 0);
++
++do_ds250dfx10_pttchk_show_ret:
++ return ret;
++}
++
++static int do_ds250dfx10_pttchk_start(void)
++{
++ int ret;
++
++ /* enable access to channel registers */
++ ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 1);
++ if (ret)
++ goto do_ds250dfx10_pttchk_start_ret;
++
++ /* enable de-serializer */
++ ret = ds250dfx10_set(DS250DFX10_REG_DES_PD, 0);
++ if (ret)
++ goto do_ds250dfx10_pttchk_start_cleanup;
++
++ /* enable prbs checker */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_CHKR_EN, 1);
++ if (ret)
++ goto do_ds250dfx10_pttchk_start_cleanup;
++
++ /* disable prbs clock (to reset if active) */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_EN_DIG_CLK, 0);
++ if (ret)
++ goto do_ds250dfx10_pttchk_start_cleanup;
++
++ /* enable prbs clock */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_EN_DIG_CLK, 1);
++ if (ret)
++ goto do_ds250dfx10_pttchk_start_cleanup;
++
++ /* reload seed */
++ ret = ds250dfx10_set(DS250DFX10_RELOAD_PRBS_CHKR, 1);
++ if (ret)
++ goto do_ds250dfx10_pttchk_start_cleanup;
++ ret = ds250dfx10_set(DS250DFX10_RELOAD_PRBS_CHKR, 0);
++ if (ret)
++ goto do_ds250dfx10_pttchk_start_cleanup;
++
++ /* reset counters */
++ ret = ds250dfx10_set(DS250DFX10_RST_PRBS_CNTS, 1);
++ if (ret)
++ goto do_ds250dfx10_pttchk_start_cleanup;
++ ret = ds250dfx10_set(DS250DFX10_RST_PRBS_CNTS, 0);
++ if (ret)
++ goto do_ds250dfx10_pttchk_start_cleanup;
++
++do_ds250dfx10_pttchk_start_cleanup:
++ /* disable access to channel registers */
++ ds250dfx10_set(DS250DFX10_EN_CH_SMB, 0);
++
++do_ds250dfx10_pttchk_start_ret:
++ return ret;
++}
++
++static int do_ds250dfx10_pttchk_stop(void)
++{
++ int ret;
++
++ /* enable access to channel registers */
++ ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 1);
++ if (ret)
++ goto do_ds250dfx10_pttchk_stop_ret;
++
++ /* disable prbs clock */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_EN_DIG_CLK, 0);
++ if (ret)
++ goto do_ds250dfx10_pttchk_stop_cleanup;
++
++ /* disable prbs checker */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_CHKR_EN, 0);
++ if (ret)
++ goto do_ds250dfx10_pttchk_stop_cleanup;
++
++ /* disable de-serializer */
++ ret = ds250dfx10_set(DS250DFX10_REG_DES_PD, 1);
++ if (ret)
++ goto do_ds250dfx10_pttchk_stop_cleanup;
++
++do_ds250dfx10_pttchk_stop_cleanup:
++ /* disable access to channel registers */
++ ds250dfx10_set(DS250DFX10_EN_CH_SMB, 0);
++
++do_ds250dfx10_pttchk_stop_ret:
++ return ret;
++}
++
++static int do_ds250dfx10_pttchk(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
++{
++ int ret;
++
++ if (!priv->dev) {
++ puts("no device selected\n");
++ return CMD_RET_FAILURE;
++ }
++
++ ret = do_ds250dfx10_chan_get();
++ if (ret < 0) {
++ return CMD_RET_FAILURE;
++ } else if (ret == 0) {
++ puts("no channel selected\n");
++ return CMD_RET_FAILURE;
++ }
++
++ if (argc != 2)
++ return CMD_RET_USAGE;
++
++ if (!strcmp(argv[1], "show"))
++ ret = do_ds250dfx10_pttchk_show();
++ else if (!strcmp(argv[1], "start"))
++ ret = do_ds250dfx10_pttchk_start();
++ else if (!strcmp(argv[1], "stop"))
++ ret = do_ds250dfx10_pttchk_stop();
++ else
++ return CMD_RET_USAGE;
++
++ return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
++}
++
++/* read data bytes and dump as csv */
++static int do_ds250dfx10_eom_csv(enum ds250dfx10_eom_vrange vrange)
++{
++ int ret = 0;
++ uint16_t val;
++
++ /* print labels */
++ printf("\"phase\",\"voltage (%s)\",\"count\"\r\n", ds250dfx10_eom_vrange_str[vrange]);
++
++ /* read and dump data */
++ for (int p = 0; p < 64; p++) {
++ for (int v = 0; v < 64; v++) {
++ ret = ds250dfx10_read(DS250DFX10_EOM_DATA_HI, (uint8_t *)&val, sizeof(val));
++ if (ret)
++ return ret;
++ val = le16_to_cpu(val);
++
++ printf("%d,%d,%u\r\n", p, v, val);
++ }
++ }
++
++ return ret;
++}
++
++static uint8_t eom_vte_colour(uint16_t count)
++{
++ if (count == 0)
++ return 40; // black
++ else if (count < 128)
++ return 46; // cyan
++ else if (count < 256)
++ return 100; // dark gray
++ else if (count < 512)
++ return 47; // light gray
++ else if (count < 1024)
++ return 107; // white
++ else if (count < 2048)
++ return 47; // light cyan
++ else if (count < 4096)
++ return 103; // light yellow
++ else if (count < 8192)
++ return 102; // light green
++ else
++ return 42; // green
++}
++
++/* read data bytes and dump to vte 256 colour terminal */
++static int do_ds250dfx10_eom_vte(enum ds250dfx10_eom_vrange vrange)
++{
++ int ret = 0;
++ uint16_t val;
++
++ puts("\e[104m\e[91m\e[1m 0------------------------------------------------------------>phase\e[0m\n");
++
++ for (int p = 0; p < 64; p++) {
++ if (p < 63)
++ puts("\e[104m\e[91m\e[1m | \e[0m");
++ else
++ puts("\e[104m\e[91m\e[1m v \e[0m");
++
++ for (int v = 0; v < 64; v++) {
++ ret = ds250dfx10_read(DS250DFX10_EOM_DATA_HI, (uint8_t *)&val, sizeof(val));
++ if (ret)
++ return ret;
++ val = le16_to_cpu(val);
++
++ printf("\e[%um \e[0m", eom_vte_colour(val));
++ }
++
++ puts("\e[104m\e[91m\e[1m \e[0m\n");
++ }
++ printf("\e[104m\e[91m\e[1mvoltage (%s)%*s\e[0m\n", ds250dfx10_eom_vrange_str[vrange], 65 - 7 - (int)strlen(ds250dfx10_eom_vrange_str[vrange]), "");
++
++ return ret;
++}
++
++static int do_ds250dfx10_eom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
++{
++ int ret;
++ uint8_t val1;
++ uint16_t val2;
++ enum ds250dfx10_eom_vrange vrange = DS250DFX10_EOM_400MV;
++ enum ds250dfx10_eom_fmt fmt;
++
++ if (!priv->dev) {
++ puts("no device selected\n");
++ return CMD_RET_FAILURE;
++ }
++
++ ret = do_ds250dfx10_chan_get();
++ if (ret < 0) {
++ return CMD_RET_FAILURE;
++ } else if (ret == 0) {
++ puts("no channel selected\n");
++ return CMD_RET_FAILURE;
++ }
++
++ if (argc != 2)
++ return CMD_RET_USAGE;
++
++ fmt = ds250dfx10_eom_fmt_parse(argv[1]);
++ if (fmt == DS250DFX10_EOM_FMT_MAX) {
++ printf("unknown format \"%s\"\n", argv[1]);
++ return CMD_RET_FAILURE;
++ }
++
++ /* enable access to channel registers */
++ ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 1);
++ if (ret)
++ goto do_ds250dfx10_eom_ret;
++
++ /* test if CDR locked */
++ ret = ds250dfx10_get(DS250DFX10_CDR_LOCK_STATUS, &val1);
++ if (ret)
++ goto do_ds250dfx10_eom_cleanup;
++ else if (!val1) {
++ puts("cdr not locked, ensure pattern generator is active and connected\n");
++ ret = -EIO;
++ goto do_ds250dfx10_eom_cleanup;
++ }
++
++ /* disable lock monitoring */
++ ret = ds250dfx10_set(DS250DFX10_HV_LOCKMON_EN, 0);
++ if (ret)
++ goto do_ds250dfx10_eom_cleanup;
++
++ /* disable automatic vertical range scaling */
++ ret = ds250dfx10_set(DS250DFX10_VEO_SCALE, 0);
++ if (ret)
++ goto do_ds250dfx10_eom_cleanup;
++
++ /* set vertical range */
++ ret = ds250dfx10_set(DS250DFX10_EOM_SEL_VRANGE, vrange);
++ if (ret)
++ goto do_ds250dfx10_eom_cleanup;
++
++ /* force enable eom */
++ ret = ds250dfx10_set(DS250DFX10_EOM_PD, 0);
++ if (ret)
++ goto do_ds250dfx10_eom_cleanup;
++
++ /* enable eom fast mode */
++ ret = ds250dfx10_set(DS250DFX10_FAST_EOM, 1);
++ if (ret)
++ goto do_ds250dfx10_eom_cleanup;
++
++ /* read eye diagram */
++ /* (re-)start counter */
++ ret = ds250dfx10_set(DS250DFX10_EOM_START, 1);
++ if (ret)
++ goto do_ds250dfx10_eom_cleanup;
++
++ /* wait for eom capture to complete */
++ do {
++ ret = ds250dfx10_get(DS250DFX10_EOM_START, &val1);
++ if (ret)
++ goto do_ds250dfx10_eom_cleanup;
++ } while (val1);
++
++ /* skip first 4 invalid data bytes */
++ for (int i = 0; i < 4; i++) {
++ ret = ds250dfx10_read(DS250DFX10_EOM_DATA_HI, (uint8_t *)&val2, sizeof(val2));
++ if (ret)
++ goto do_ds250dfx10_eom_cleanup;
++ }
++
++ switch (fmt) {
++ case DS250DFX10_CSV:
++ ret = do_ds250dfx10_eom_csv(vrange);
++ break;
++ case DS250DFX10_VTE:
++ ret = do_ds250dfx10_eom_vte(vrange);
++ break;
++ default:
++ ret = 0;
++ break;
++ }
++ if (ret)
++ goto do_ds250dfx10_eom_cleanup;
++
++ /* disable eom fast mode */
++ ret = ds250dfx10_set(DS250DFX10_FAST_EOM, 0);
++
++ /* return eom to automatic mode */
++ ret = ds250dfx10_set(DS250DFX10_EOM_PD, 1);
++
++ /* (re-)enable automatic vrange scaling */
++ ret = ds250dfx10_set(DS250DFX10_VEO_SCALE, 1);
++
++ /* (re-)enable lock monitoring */
++ ret = ds250dfx10_set(DS250DFX10_HV_LOCKMON_EN, 0);
++
++do_ds250dfx10_eom_cleanup:
++ /* disable access to channel registers */
++ ds250dfx10_set(DS250DFX10_EN_CH_SMB, 0);
++
++do_ds250dfx10_eom_ret:
++ return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
++}
++
++static int do_ds250dfx10_todo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
++{
++ for (int i = 0; i < argc; i++) {
++ if (i)
++ putc(' ');
++
++ puts(argv[i]);
++ }
++ putc('\n');
++
++ return CMD_RET_SUCCESS;
++}
++
++/*
++ * Example usage on LX2162 Clearfog, loopback on DPMAC6 (bottom left SFP near power):
++ *
++ * => ds250dfx10 dev i2c at 2020000 0x18
++ * => ds250dfx10 chan 0
++ * => ds250dfx10 pttgen PRBS7
++ * => ds250dfx10 chan 1
++ * => ds250dfx10 pttchk start
++ * => ds250dfx10 pttchk show
++ * => ds250dfx10 eom VTE
++ */
++
++U_BOOT_LONGHELP(ds250dfx10,
++ "ds250dfx10 dev [<i2c bus name> <i2c bus address>] - select active retimer device\n"
++ "ds250dfx10 chan [<channel>] - get/set current retimer channel\n"
++ "ds250dfx10 pttgen <pattern> - start pattern generator\n"
++ " - <pattern> is one of [ PRBS7, PRBS9, PRBS11, PRBS15, PRBS23, PRBS31, PRBS58, PRBS63]\n"
++ "ds250dfx10 pttgen stop - stop pattern generator\n"
++ "ds250dfx10 pttchk show - print pattern checker results\n"
++ "ds250dfx10 pttchk start - start pattern checker\n"
++ "ds250dfx10 pttchk stop - stop pattern checker\n"
++ "ds250dfx10 eom <format> - capture eye diagram\n"
++ " <format> is one of [ CSV, VTE ]\n"
++ " - CSV: comma separated values dumped on terminal\n"
++ " - VTE: draw diagram on terminal with colours\n"
++ "ds250dfx10 todo - to be done\n");
++
++U_BOOT_CMD_WITH_SUBCMDS(ds250dfx10, "DS250DFx10 Retimer", ds250dfx10_help_text,
++ U_BOOT_SUBCMD_MKENT(dev, 3, 1, do_ds250dfx10_dev),
++ U_BOOT_SUBCMD_MKENT(chan, 2, 1, do_ds250dfx10_chan),
++ U_BOOT_SUBCMD_MKENT(pttgen, 2, 1, do_ds250dfx10_pttgen),
++ U_BOOT_SUBCMD_MKENT(pttchk, 2, 1, do_ds250dfx10_pttchk),
++ U_BOOT_SUBCMD_MKENT(eom, 2, 1, do_ds250dfx10_eom),
++ U_BOOT_SUBCMD_MKENT(todo, 100, 1, do_ds250dfx10_todo));
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 461abb76af2..72072756f26 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -43,6 +43,7 @@ CONFIG_CMD_PCI=y
+ CONFIG_CMD_POWEROFF=y
+ CONFIG_CMD_USB=y
+ CONFIG_CMD_WDT=y
++CONFIG_CMD_DS250DFX10=y
+ CONFIG_OF_CONTROL=y
+ CONFIG_ENV_OVERWRITE=y
+ CONFIG_ENV_IS_IN_MMC=y
+--
+2.51.0
+
diff --git a/board/solidrun/lx2160acex7/patches/uboot/0027-cmd-ds250dfx10-add-prbs-validation-command-for-timed.patch b/board/solidrun/lx2160acex7/patches/uboot/0027-cmd-ds250dfx10-add-prbs-validation-command-for-timed.patch
new file mode 100644
index 0000000000..7b5256f9f1
--- /dev/null
+++ b/board/solidrun/lx2160acex7/patches/uboot/0027-cmd-ds250dfx10-add-prbs-validation-command-for-timed.patch
@@ -0,0 +1,938 @@
+From ab33c4ff05ca138d3a62eabf073088643d40ff72 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua at solid-run.com>
+Date: Tue, 2 Sep 2025 16:46:31 +0200
+Subject: [PATCH] cmd: ds250dfx10: add prbs validation command for timed error
+ counting
+
+Implement a validation command using the prbs checker feature to check
+prbs pattern and count errors for a given duration of time.
+
+The command does detect cdr loss to avoid invalid results.
+
+Signed-off-by: Josua Mayer <josua at solid-run.com>
+---
+ cmd/ds250dfx10.c | 613 +++++++++++++++++++++++++++++++----------------
+ 1 file changed, 401 insertions(+), 212 deletions(-)
+
+diff --git a/cmd/ds250dfx10.c b/cmd/ds250dfx10.c
+index 4977b56e66b..149c92476a1 100644
+--- a/cmd/ds250dfx10.c
++++ b/cmd/ds250dfx10.c
+@@ -4,47 +4,61 @@
+ */
+
+ #include <command.h>
++#include <console.h>
+ #include <dm/device.h>
+ #include <dm/uclass.h>
+ #include <i2c.h>
++#include <linux/delay.h>
++#include <time.h>
++
++enum ds250dfx10_reg_type {
++ DS250DFX10_REG_GLOBAL,
++ DS250DFX10_REG_SHARED,
++ DS250DFX10_REG_CHANNEL,
++ DS250DFX10_REG_TYPE_MAX,
++};
+
+-/* DS250DFx10 Shared Registers reg offset length */
+-
+-/* DS250DFx10 Channel Registers reg offset length */
+-#define DS250DFX10_REG_POL_INV_DET 0x01, 6, 1
+-#define DS250DFX10_REG_PRBS_SEQ_DET 0x01, 1, 4
+-#define DS250DFX10_REG_BYPASS_PFD_OV 0x09, 5, 1
+-#define DS250DFX10_REG_DES_PD 0x0D, 7, 1
+-#define DS250DFX10_EOM_PD 0x11, 5, 1
+-#define DS250DFX10_EOM_SEL_VRANGE 0x11, 6, 2
+-#define DS250DFX10_SER_EN 0x1E, 4, 1
+-#define DS250DFX10_PFD_SEL_DATA_PRELCK 0x1E, 5, 3
+-#define DS250DFX10_EOM_START 0x24, 0, 1
+-#define DS250DFX10_FAST_EOM 0x24, 7, 1
+-#define DS250DFX10_EOM_DATA_HI 0x25, 0, 8
+-#define DS250DFX10_EOM_DATA_LO 0x26, 0, 8
+-#define DS250DFX10_VEO_SCALE 0x2C, 6, 1
+-#define DS250DFX10_PRBS_PATTERN_SEL_HI 0x2E, 2, 1
+-#define DS250DFX10_PRBS_PATTERN_SEL_LO 0x30, 0, 2
+-#define DS250DFX10_PRBS_EN_DIG_CLK 0x30, 3, 1
+-#define DS250DFX10_RELOAD_PRBS_CHKR 0x30, 4, 1
+-#define DS250DFX10_HV_LOCKMON_EN 0x67, 5, 1
+-#define DS250DFX10_CDR_LOCK_STATUS 0x78, 4, 1
+-#define DS250DFX10_PRBS_GEN_EN 0x79, 5, 1
+-#define DS250DFX10_PRBS_CHKR_EN 0x79, 6, 1
+-#define DS250DFX10_RST_PRBS_CNTS 0x82, 6, 1
+-#define DS250DFX10_FREEZE_PRBS_CNTR 0x82, 7, 1
+-#define DS250DFX10_PRBS_ERR_CNT_HI 0x83, 0, 3
+-#define DS250DFX10_PRBS_ERR_CNT_LO 0x84, 0, 8
+-
+-/* DS250DFx10 Global Registers reg offset length */
+-#define DS250DFX10_CHAN_CONFIG_ID 0xEF, 0, 4
+-#define DS250DFX10_DEVICE_ID 0xF1, 0, 8
+-#define DS250DFX10_EN_CH(n) 0xFC, n, 1
+-#define DS250DFX10_VENDOR_ID 0xFE, 0, 8
+-#define DS250DFX10_EN_SHARE_Q0 0xFF, 4, 1
+-#define DS250DFX10_EN_SHARE_Q1 0xFF, 5, 1
+-#define DS250DFX10_EN_CH_SMB 0xFF, 0, 1
++/* DS250DFx10 Shared Registers domain, reg offset length */
++
++/* DS250DFx10 Channel Registers domain, reg offset length */
++#define DS250DFX10_CDR_LOCK_LOSS_INT DS250DFX10_REG_CHANNEL, 0x01, 5, 1
++#define DS250DFX10_POL_INV_DET DS250DFX10_REG_CHANNEL, 0x01, 6, 1
++#define DS250DFX10_PRBS_SEQ_DET DS250DFX10_REG_CHANNEL, 0x01, 1, 4
++#define DS250DFX10_BYPASS_PFD_OV DS250DFX10_REG_CHANNEL, 0x09, 5, 1
++#define DS250DFX10_DES_PD DS250DFX10_REG_CHANNEL, 0x0D, 7, 1
++#define DS250DFX10_EOM_PD DS250DFX10_REG_CHANNEL, 0x11, 5, 1
++#define DS250DFX10_EOM_SEL_VRANGE DS250DFX10_REG_CHANNEL, 0x11, 6, 2
++#define DS250DFX10_SER_EN DS250DFX10_REG_CHANNEL, 0x1E, 4, 1
++#define DS250DFX10_PFD_SEL_DATA_PRELCK DS250DFX10_REG_CHANNEL, 0x1E, 5, 3
++#define DS250DFX10_EOM_START DS250DFX10_REG_CHANNEL, 0x24, 0, 1
++#define DS250DFX10_FAST_EOM DS250DFX10_REG_CHANNEL, 0x24, 7, 1
++#define DS250DFX10_EOM_DATA_HI DS250DFX10_REG_CHANNEL, 0x25, 0, 8
++#define DS250DFX10_EOM_DATA_LO DS250DFX10_REG_CHANNEL, 0x26, 0, 8
++#define DS250DFX10_VEO_SCALE DS250DFX10_REG_CHANNEL, 0x2C, 6, 1
++#define DS250DFX10_PRBS_PATTERN_SEL_HI DS250DFX10_REG_CHANNEL, 0x2E, 2, 1
++#define DS250DFX10_PRBS_PATTERN_SEL_LO DS250DFX10_REG_CHANNEL, 0x30, 0, 2
++#define DS250DFX10_PRBS_EN_DIG_CLK DS250DFX10_REG_CHANNEL, 0x30, 3, 1
++#define DS250DFX10_RELOAD_PRBS_CHKR DS250DFX10_REG_CHANNEL, 0x30, 4, 1
++#define DS250DFX10_SIGNAL_DET_LOSS_INT_EN DS250DFX10_REG_CHANNEL, 0x31, 0, 1
++#define DS250DFX10_CDR_LOCK_LOSS_INT_EN DS250DFX10_REG_CHANNEL, 0x31, 1, 1
++#define DS250DFX10_PRBS_INT_EN DS250DFX10_REG_CHANNEL, 0x31, 7, 1
++#define DS250DFX10_HV_LOCKMON_EN DS250DFX10_REG_CHANNEL, 0x67, 5, 1
++#define DS250DFX10_CDR_LOCK_STATUS DS250DFX10_REG_CHANNEL, 0x78, 4, 1
++#define DS250DFX10_PRBS_GEN_EN DS250DFX10_REG_CHANNEL, 0x79, 5, 1
++#define DS250DFX10_PRBS_CHKR_EN DS250DFX10_REG_CHANNEL, 0x79, 6, 1
++#define DS250DFX10_RST_PRBS_CNTS DS250DFX10_REG_CHANNEL, 0x82, 6, 1
++#define DS250DFX10_FREEZE_PRBS_CNTR DS250DFX10_REG_CHANNEL, 0x82, 7, 1
++#define DS250DFX10_PRBS_ERR_CNT_HI DS250DFX10_REG_CHANNEL, 0x83, 0, 3
++#define DS250DFX10_PRBS_ERR_CNT_LO DS250DFX10_REG_CHANNEL, 0x84, 0, 8
++
++/* DS250DFx10 Global Registers domain, reg offset length */
++#define DS250DFX10_CHAN_CONFIG_ID DS250DFX10_REG_GLOBAL, 0xEF, 0, 4
++#define DS250DFX10_DEVICE_ID DS250DFX10_REG_GLOBAL, 0xF1, 0, 8
++#define DS250DFX10_EN_CH(n) DS250DFX10_REG_GLOBAL, 0xFC, n, 1
++#define DS250DFX10_VENDOR_ID DS250DFX10_REG_GLOBAL, 0xFE, 0, 8
++#define DS250DFX10_EN_SHARE_Q0 DS250DFX10_REG_GLOBAL, 0xFF, 4, 1
++#define DS250DFX10_EN_SHARE_Q1 DS250DFX10_REG_GLOBAL, 0xFF, 5, 1
++#define DS250DFX10_EN_CH_SMB DS250DFX10_REG_GLOBAL, 0xFF, 0, 1
+
+ enum ds250dfx10_type {
+ DS250DF410 = 0,
+@@ -135,21 +149,47 @@ static enum ds250dfx10_eom_fmt ds250dfx10_eom_fmt_parse(const char *const str)
+ static struct _ds250dfx10_priv {
+ struct udevice *dev;
+ enum ds250dfx10_type type;
++ bool sel_chan_regs;
+ } _priv;
+ static struct _ds250dfx10_priv *const priv = &_priv;
+
+-inline int ds250dfx10_read(uint8_t reg, uint8_t, uint8_t, uint8_t *const buffer, const uint8_t len)
++static int ds250dfx10_read(const enum ds250dfx10_reg_type type, const uint8_t reg, const uint8_t, const uint8_t, uint8_t *const buffer, const uint8_t len);
++static int ds250dfx10_write(const enum ds250dfx10_reg_type type, const uint8_t reg, const uint8_t, const uint8_t, const uint8_t *const buffer, const uint8_t len);
++
++static int ds250dfx10_get(enum ds250dfx10_reg_type type, const uint8_t reg, const uint8_t offset, const uint8_t len, uint8_t *const val);
++static int ds250dfx10_set(enum ds250dfx10_reg_type type, const uint8_t reg, const uint8_t offset, const uint8_t len, const uint8_t val);
++
++static inline int ds250dfx10_sel_reg_type(const enum ds250dfx10_reg_type type);
++
++static int ds250dfx10_read(const enum ds250dfx10_reg_type type, const uint8_t reg, const uint8_t, const uint8_t, uint8_t *const buffer, const uint8_t len)
+ {
++ int ret;
++
++ ret = ds250dfx10_sel_reg_type(type);
++ if (ret)
++ return ret;
++
+ return dm_i2c_read(priv->dev, reg, buffer, len);
+ }
+
+-static int ds250dfx10_get(const uint8_t reg, const uint8_t offset, const uint8_t len, uint8_t *const val)
++static int ds250dfx10_write(const enum ds250dfx10_reg_type type, const uint8_t reg, const uint8_t, const uint8_t, const uint8_t *const buffer, const uint8_t len)
++{
++ int ret;
++
++ ret = ds250dfx10_sel_reg_type(type);
++ if (ret)
++ return ret;
++
++ return dm_i2c_write(priv->dev, reg, buffer, len);
++}
++
++static int ds250dfx10_get(enum ds250dfx10_reg_type type, const uint8_t reg, const uint8_t offset, const uint8_t len, uint8_t *const val)
+ {
+ int ret;
+ const uint8_t mask = ((2 << (len - 1)) - 1) << offset;
+ uint8_t _val = 0;
+
+- ret = dm_i2c_read(priv->dev, reg, &_val, sizeof(_val));
++ ret = ds250dfx10_read(type, reg, offset, len, &_val, sizeof(_val));
+ if (ret) {
+ printf("failed to read register %#04x: %d\n", reg, ret);
+ return ret;
+@@ -161,13 +201,13 @@ static int ds250dfx10_get(const uint8_t reg, const uint8_t offset, const uint8_t
+ return 0;
+ }
+
+-static int ds250dfx10_set(const uint8_t reg, const uint8_t offset, const uint8_t len, const uint8_t val)
++static int ds250dfx10_set(enum ds250dfx10_reg_type type, const uint8_t reg, const uint8_t offset, const uint8_t len, const uint8_t val)
+ {
+ int ret;
+ const uint8_t mask = ((2 << (len - 1)) - 1) << offset;
+ uint8_t _val = 0;
+
+- ret = dm_i2c_read(priv->dev, reg, &_val, sizeof(_val));
++ ret = ds250dfx10_read(type, reg, offset, len, &_val, sizeof(_val));
+ if (ret) {
+ printf("failed to read register %#04x: %d\n", reg, ret);
+ return ret;
+@@ -176,7 +216,7 @@ static int ds250dfx10_set(const uint8_t reg, const uint8_t offset, const uint8_t
+ _val &= ~mask;
+ _val |= (val << offset) & mask;
+
+- dm_i2c_write(priv->dev, reg, &_val, sizeof(_val));
++ ret = ds250dfx10_write(type, reg, offset, len, &_val, sizeof(_val));
+ if (ret)
+ printf("failed to write register %#04x = %#04x: %d\n", reg, _val, ret);
+ //printf("dm_i2c_write %#04x = %#04x\n", reg, _val);
+@@ -184,13 +224,34 @@ static int ds250dfx10_set(const uint8_t reg, const uint8_t offset, const uint8_t
+ return ret;
+ }
+
++static inline int ds250dfx10_sel_reg_type(const enum ds250dfx10_reg_type type)
++{
++ int ret;
++
++ if (type == DS250DFX10_REG_SHARED && priv->sel_chan_regs) {
++ ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 0);
++ if (ret)
++ return ret;
++
++ priv->sel_chan_regs = false;
++ } else if (type == DS250DFX10_REG_CHANNEL && !priv->sel_chan_regs) {
++ ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 1);
++ if (ret)
++ return ret;
++
++ priv->sel_chan_regs = true;
++ }
++
++ return 0;
++}
++
+ static int do_ds250dfx10_dev(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+ {
+ const char * _bus;
+ struct udevice *bus;
+ unsigned long _addr;
+ unsigned int addr;
+- uint8_t vendor_id, device_id, chan_conf;
++ uint8_t vendor_id, device_id, chan_conf, sel_chan_regs;;
+ int ret;
+
+ switch (argc) {
+@@ -246,6 +307,14 @@ static int do_ds250dfx10_dev(struct cmd_tbl *cmdtp, int flag, int argc, char *co
+ return CMD_RET_FAILURE;
+ }
+
++ /* read whether channel registers are selected */
++ ret = ds250dfx10_get(DS250DFX10_EN_CH_SMB, &sel_chan_regs);
++ if (ret < 0) {
++ priv->dev = NULL;
++ return CMD_RET_FAILURE;
++ }
++ priv->sel_chan_regs = !!sel_chan_regs;
++
+ if (!priv->dev) {
+ puts("no retimer selected\n");
+ return CMD_RET_FAILURE;
+@@ -343,48 +412,37 @@ static int do_ds250dfx10_pttgen_stop(void)
+ int ret;
+ uint8_t val;
+
+- /* enable access to channel registers */
+- ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 1);
+- if (ret)
+- goto do_ds250dfx10_pttgen_stop_ret;
+-
+ /* confirm generator is active */
+ ret = ds250dfx10_get(DS250DFX10_PRBS_GEN_EN, &val);
+ if (ret) {
+- goto do_ds250dfx10_pttgen_stop_cleanup;
++ return ret;
+ } else if (!val) {
+ puts("prbs generator not active\n");
+- ret = -EINVAL;
+- goto do_ds250dfx10_pttgen_stop_cleanup;
++ return -EINVAL;
+ }
+
+ /* disable output override */
+- ret = ds250dfx10_set(DS250DFX10_REG_BYPASS_PFD_OV, 0);
++ ret = ds250dfx10_set(DS250DFX10_BYPASS_PFD_OV, 0);
+ if (ret)
+- goto do_ds250dfx10_pttgen_stop_cleanup;
++ return ret;
+
+ /* disable prbs generator */
+ ret = ds250dfx10_set(DS250DFX10_PRBS_GEN_EN, 0);
+ if (ret)
+- goto do_ds250dfx10_pttgen_stop_cleanup;
++ return ret;
+
+ /* disable prbs clock */
+ ret = ds250dfx10_set(DS250DFX10_PRBS_EN_DIG_CLK, 0);
+ if (ret)
+- goto do_ds250dfx10_pttgen_stop_cleanup;
++ return ret;
+
+ /* disable serializer */
+ ret = ds250dfx10_set(DS250DFX10_SER_EN, 0);
+ if (ret)
+- goto do_ds250dfx10_pttgen_stop_cleanup;
++ return ret;
+
+ puts("prbs generator stopped\n");
+
+-do_ds250dfx10_pttgen_stop_cleanup:
+- /* disable access to channel registers */
+- ds250dfx10_set(DS250DFX10_EN_CH_SMB, 0);
+-
+-do_ds250dfx10_pttgen_stop_ret:
+ return ret;
+ }
+
+@@ -399,62 +457,52 @@ static int do_ds250dfx10_pttgen_start(const enum ds250dfx10_prbs_pattern prbs_pt
+ enum ds250dfx10_prbs_pattern sel;
+ } prbs_ptt_sel = { .sel = prbs_ptt };
+
+- /* enable access to channel registers */
+- ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 1);
+- if (ret)
+- goto do_ds250dfx10_pttgen_start_ret;
+-
+ /* select pattern */
+ ret = ds250dfx10_set(DS250DFX10_PRBS_PATTERN_SEL_HI, prbs_ptt_sel.bits.hi);
+ if (ret)
+- goto do_ds250dfx10_pttgen_start_cleanup;
++ return ret;
+
+ ret = ds250dfx10_set(DS250DFX10_PRBS_PATTERN_SEL_LO, prbs_ptt_sel.bits.lo);
+ if (ret)
+- goto do_ds250dfx10_pttgen_start_cleanup;
++ return ret;
+
+ /* enable serializer */
+ ret = ds250dfx10_set(DS250DFX10_SER_EN, 1);
+ if (ret)
+- goto do_ds250dfx10_pttgen_start_cleanup;
++ return ret;
+
+ /* disable prbs generator (to reset if active) */
+ ret = ds250dfx10_set(DS250DFX10_PRBS_GEN_EN, 0);
+ if (ret)
+- goto do_ds250dfx10_pttgen_start_cleanup;
++ return ret;
+
+ /* enable prbs generator */
+ ret = ds250dfx10_set(DS250DFX10_PRBS_GEN_EN, 1);
+ if (ret)
+- goto do_ds250dfx10_pttgen_start_cleanup;
++ return ret;
+
+ /* disable prbs clock (to reset if active) */
+ ret = ds250dfx10_set(DS250DFX10_PRBS_EN_DIG_CLK, 0);
+ if (ret)
+- goto do_ds250dfx10_pttgen_start_cleanup;
++ return ret;
+
+ /* enable prbs clock */
+ ret = ds250dfx10_set(DS250DFX10_PRBS_EN_DIG_CLK, 1);
+ if (ret)
+- goto do_ds250dfx10_pttgen_start_cleanup;
++ return ret;
+
+ /* enable prbs generator output */
+ ret = ds250dfx10_set(DS250DFX10_PFD_SEL_DATA_PRELCK, 4);
+ if (ret)
+- goto do_ds250dfx10_pttgen_start_cleanup;
++ return ret;
+
+ /* enable output override */
+- ret = ds250dfx10_set(DS250DFX10_REG_BYPASS_PFD_OV, 1);
++ ret = ds250dfx10_set(DS250DFX10_BYPASS_PFD_OV, 1);
+ if (ret)
+- goto do_ds250dfx10_pttgen_start_cleanup;
++ return ret;
+
+ printf("PRBS generator started with %s\n", ds250dfx10_prbs_pattern_str[prbs_ptt]);
+
+-do_ds250dfx10_pttgen_start_cleanup:
+- /* disable access to channel registers */
+- ds250dfx10_set(DS250DFX10_EN_CH_SMB, 0);
+-
+-do_ds250dfx10_pttgen_start_ret:
+ return ret;
+ }
+
+@@ -502,150 +550,290 @@ static int do_ds250dfx10_pttgen(struct cmd_tbl *cmdtp, int flag, int argc, char
+ return CMD_RET_SUCCESS;
+ }
+
+-static int do_ds250dfx10_pttchk_show(void)
++static int ds250dfx10_pttchk_enable(void)
+ {
+ int ret;
+- uint8_t val1;
+- uint16_t val2;
+- enum ds250dfx10_prbs_pattern prbs_ptt;
+-
+- /* enable access to channel registers */
+- ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 1);
+- if (ret)
+- goto do_ds250dfx10_pttchk_show_ret;
+-
+- /* read detected pattern */
+- ret = ds250dfx10_get(DS250DFX10_REG_PRBS_SEQ_DET, &val1);
+- if (ret) {
+- goto do_ds250dfx10_pttchk_show_cleanup;
+- } else if (!(val1 & 0x08)) {
+- printf("no pattern detected\n");
+- goto do_ds250dfx10_pttchk_show_cleanup;
+- }
+- prbs_ptt = val1 & 0x07;
+
+- /* read polarity */
+- ret = ds250dfx10_get(DS250DFX10_REG_POL_INV_DET, &val1);
+- if (ret)
+- goto do_ds250dfx10_pttchk_show_cleanup;
+-
+- puts("detected ");
+- puts(ds250dfx10_prbs_pattern_str[prbs_ptt]);
+- if (val1)
+- puts(", polarity inverted");
+- putc('\n');
+-
+- /* freeze error counter */
+- ret = ds250dfx10_set(DS250DFX10_FREEZE_PRBS_CNTR, 1);
++ /* enable de-serializer */
++ ret = ds250dfx10_set(DS250DFX10_DES_PD, 0);
+ if (ret)
+- goto do_ds250dfx10_pttchk_show_cleanup;
++ return ret;
+
+- /* read error counter */
+- ret = ds250dfx10_read(DS250DFX10_PRBS_ERR_CNT_HI, (uint8_t *)&val2, sizeof(val2));
++ /* enable prbs checker */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_CHKR_EN, 1);
+ if (ret)
+- goto do_ds250dfx10_pttchk_show_cleanup;
+- val2 &= 0x07FF;
++ return ret;
+
+- /* release error counter */
+- ret = ds250dfx10_set(DS250DFX10_FREEZE_PRBS_CNTR, 0);
++ /* enable prbs clock */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_EN_DIG_CLK, 1);
+ if (ret)
+- goto do_ds250dfx10_pttchk_show_cleanup;
+-
+- printf("errors: %u\n", val2);
+-
+-do_ds250dfx10_pttchk_show_cleanup:
+- /* disable access to channel registers */
+- ds250dfx10_set(DS250DFX10_EN_CH_SMB, 0);
++ return ret;
+
+-do_ds250dfx10_pttchk_show_ret:
+ return ret;
+ }
+
+-static int do_ds250dfx10_pttchk_start(void)
++static int ds250dfx10_pttchk_reset(void)
+ {
+ int ret;
+
+- /* enable access to channel registers */
+- ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 1);
+- if (ret)
+- goto do_ds250dfx10_pttchk_start_ret;
+-
+- /* enable de-serializer */
+- ret = ds250dfx10_set(DS250DFX10_REG_DES_PD, 0);
+- if (ret)
+- goto do_ds250dfx10_pttchk_start_cleanup;
+-
+- /* enable prbs checker */
+- ret = ds250dfx10_set(DS250DFX10_PRBS_CHKR_EN, 1);
+- if (ret)
+- goto do_ds250dfx10_pttchk_start_cleanup;
+-
+ /* disable prbs clock (to reset if active) */
+ ret = ds250dfx10_set(DS250DFX10_PRBS_EN_DIG_CLK, 0);
+ if (ret)
+- goto do_ds250dfx10_pttchk_start_cleanup;
++ return ret;
+
+ /* enable prbs clock */
+ ret = ds250dfx10_set(DS250DFX10_PRBS_EN_DIG_CLK, 1);
+ if (ret)
+- goto do_ds250dfx10_pttchk_start_cleanup;
++ return ret;
+
+ /* reload seed */
+ ret = ds250dfx10_set(DS250DFX10_RELOAD_PRBS_CHKR, 1);
+ if (ret)
+- goto do_ds250dfx10_pttchk_start_cleanup;
++ return ret;
+ ret = ds250dfx10_set(DS250DFX10_RELOAD_PRBS_CHKR, 0);
+ if (ret)
+- goto do_ds250dfx10_pttchk_start_cleanup;
++ return ret;
+
+ /* reset counters */
+ ret = ds250dfx10_set(DS250DFX10_RST_PRBS_CNTS, 1);
+ if (ret)
+- goto do_ds250dfx10_pttchk_start_cleanup;
++ return ret;
+ ret = ds250dfx10_set(DS250DFX10_RST_PRBS_CNTS, 0);
+ if (ret)
+- goto do_ds250dfx10_pttchk_start_cleanup;
+-
+-do_ds250dfx10_pttchk_start_cleanup:
+- /* disable access to channel registers */
+- ds250dfx10_set(DS250DFX10_EN_CH_SMB, 0);
++ return ret;
+
+-do_ds250dfx10_pttchk_start_ret:
+ return ret;
+ }
+
+-static int do_ds250dfx10_pttchk_stop(void)
++static int ds250dfx10_pttchk_disable(void)
+ {
+ int ret;
+
+- /* enable access to channel registers */
+- ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 1);
+- if (ret)
+- goto do_ds250dfx10_pttchk_stop_ret;
+-
+ /* disable prbs clock */
+ ret = ds250dfx10_set(DS250DFX10_PRBS_EN_DIG_CLK, 0);
+ if (ret)
+- goto do_ds250dfx10_pttchk_stop_cleanup;
++ return ret;
+
+ /* disable prbs checker */
+ ret = ds250dfx10_set(DS250DFX10_PRBS_CHKR_EN, 0);
+ if (ret)
+- goto do_ds250dfx10_pttchk_stop_cleanup;
++ return ret;
+
+ /* disable de-serializer */
+- ret = ds250dfx10_set(DS250DFX10_REG_DES_PD, 1);
++ ret = ds250dfx10_set(DS250DFX10_DES_PD, 1);
+ if (ret)
+- goto do_ds250dfx10_pttchk_stop_cleanup;
+-
+-do_ds250dfx10_pttchk_stop_cleanup:
+- /* disable access to channel registers */
+- ds250dfx10_set(DS250DFX10_EN_CH_SMB, 0);
++ return ret;
+
+-do_ds250dfx10_pttchk_stop_ret:
+ return ret;
+ }
+
++static int ds250dfx10_pttchk_get_pattern(enum ds250dfx10_prbs_pattern *const prbs_ptt, bool *const pol_inv)
++{
++ int ret;
++ uint8_t val1;
++
++ /* read detected pattern */
++ ret = ds250dfx10_get(DS250DFX10_PRBS_SEQ_DET, &val1);
++ if (ret)
++ return ret;
++ else if (!(val1 & 0x08))
++ *prbs_ptt = DS250DFX10_PRBS_PATTERN_MAX;
++ else
++ *prbs_ptt = val1 & 0x07;
++
++ /* read polarity */
++ ret = ds250dfx10_get(DS250DFX10_POL_INV_DET, &val1);
++ if (ret)
++ return ret;
++ *pol_inv = !!val1;
++
++ return 0;
++}
++
++static int ds250dfx10_pttchk_get_pattern_wait(enum ds250dfx10_prbs_pattern *const prbs_ptt, bool *const pol_inv, const unsigned long timeout)
++{
++ int ret;
++ const unsigned long start = get_timer(0);
++
++ while (1) {
++ /* read detected pattern */
++ ret = ds250dfx10_pttchk_get_pattern(prbs_ptt, pol_inv);
++ if (ret) {
++ return ret;
++ } else if (*prbs_ptt != DS250DFX10_PRBS_PATTERN_MAX) {
++ return 0;
++ } else if(get_timer(start) > timeout) {
++ return -ETIMEDOUT;
++ } else if (ctrlc()) {
++ puts("<INTERRUPT>\n");
++ return -EINTR;
++ }
++
++ udelay(1);
++ schedule();
++ };
++}
++
++static int ds250dfx10_pttchk_get_errors(uint16_t *const count)
++{
++ int ret;
++ uint16_t val2;
++
++ /* freeze error counter */
++ ret = ds250dfx10_set(DS250DFX10_FREEZE_PRBS_CNTR, 1);
++ if (ret)
++ return ret;
++
++ /* read error counter */
++ ret = ds250dfx10_read(DS250DFX10_PRBS_ERR_CNT_HI, (uint8_t *)&val2, sizeof(val2));
++ if (ret)
++ return ret;
++ val2 &= 0x07FF;
++
++ /* release error counter */
++ ret = ds250dfx10_set(DS250DFX10_FREEZE_PRBS_CNTR, 0);
++ if (ret)
++ return ret;
++
++ *count = le16_to_cpu(val2);
++
++ return 0;
++}
++
++static int do_ds250dfx10_pttchk_detect(const unsigned long timeout)
++{
++ int ret;
++ uint8_t val1;
++ bool pol_inv;
++ enum ds250dfx10_prbs_pattern prbs_ptt;
++
++ /* test if pattern checker is enabled */
++ ret = ds250dfx10_get(DS250DFX10_PRBS_CHKR_EN, &val1);
++ if (ret) {
++ return CMD_RET_FAILURE;
++ } else if (!val1) {
++ puts("pattern checker not started\n");
++ return CMD_RET_FAILURE;
++ }
++
++ /* reset pattern checker */
++ ret = ds250dfx10_pttchk_reset();
++ if (ret)
++ return CMD_RET_FAILURE;
++
++ /* wait for pattern detection */
++ puts("detecting pattern ...");
++ ret = ds250dfx10_pttchk_get_pattern_wait(&prbs_ptt, &pol_inv, timeout);
++ if (ret) {
++ printf(" failed: %d\n", ret);
++ return CMD_RET_FAILURE;
++ }
++
++ puts(" done: ");
++ puts(ds250dfx10_prbs_pattern_str[prbs_ptt]);
++ if (pol_inv)
++ puts(", polarity inverted");
++ putc('\n');
++
++ return CMD_RET_SUCCESS;
++}
++
++/* measure loss over period of time */
++int do_ds250dfx10_pttchk_validate(long duration)
++{
++ int ret;
++ uint8_t val1;
++ uint16_t errors;
++ unsigned long start;
++ const unsigned long pattern_detect_timeout = 1 * 1000; // 1 second
++ const unsigned long duration_ms = duration * 1000;
++
++ /* test if pattern checker is enabled */
++ ret = ds250dfx10_get(DS250DFX10_PRBS_CHKR_EN, &val1);
++ if (ret) {
++ goto do_ds250dfx10_pttchk_validate_ret;
++ } else if (!val1) {
++ puts("pattern checker not started\n");
++ ret = -EINVAL;
++ goto do_ds250dfx10_pttchk_validate_ret;
++ }
++
++ /* test if CDR locked */
++ ret = ds250dfx10_get(DS250DFX10_CDR_LOCK_STATUS, &val1);
++ if (ret) {
++ goto do_ds250dfx10_pttchk_validate_ret;
++ } else if (!val1) {
++ puts("cdr not locked\n");
++ ret = -EIO;
++ goto do_ds250dfx10_pttchk_validate_ret;
++ }
++
++ /* clear cdr lock loss indication */
++ ret = ds250dfx10_get(DS250DFX10_CDR_LOCK_LOSS_INT, &val1);
++ if (ret)
++ goto do_ds250dfx10_pttchk_validate_ret;
++
++ /* enable prbs interrupts */
++ ret = ds250dfx10_set(DS250DFX10_PRBS_INT_EN, 1);
++ if (ret)
++ goto do_ds250dfx10_pttchk_validate_ret;
++
++ /* enable cdr lock loss indication */
++ ret = ds250dfx10_set(DS250DFX10_CDR_LOCK_LOSS_INT_EN, 1);
++ if (ret)
++ goto do_ds250dfx10_pttchk_validate_prbs_int;
++
++ /* reset pattern checker */
++ ret = ds250dfx10_pttchk_reset();
++
++ /* wait for pattern detection */
++ ret = do_ds250dfx10_pttchk_detect(pattern_detect_timeout);
++ if (ret != CMD_RET_SUCCESS)
++ goto do_ds250dfx10_pttchk_validate_cdr_lock_loss_int;
++
++ /* wait <duration> and count errors */
++ printf("waiting %lus ...", duration);
++ start = get_timer(0);
++ while (get_timer(start) < duration_ms) {
++ udelay(1);
++ schedule();
++
++ if (ctrlc()) {
++ puts(" <INTERRUPT>\n");
++ ret = -EINTR;
++ goto do_ds250dfx10_pttchk_validate_cdr_lock_loss_int;
++ }
++
++ /* read cdr lock loss indication */
++ ret = ds250dfx10_get(DS250DFX10_CDR_LOCK_LOSS_INT, &val1);
++ if (ret) {
++ goto do_ds250dfx10_pttchk_validate_cdr_lock_loss_int;
++ } else if (val1) {
++ puts(" failed: lost cdr lock\n");
++ ret = -EIO;
++ goto do_ds250dfx10_pttchk_validate_cdr_lock_loss_int;
++ }
++ };
++
++ /* read error counter */
++ ret = ds250dfx10_pttchk_get_errors(&errors);
++ if (ret)
++ goto do_ds250dfx10_pttchk_validate_cdr_lock_loss_int;
++
++ printf(" done: %u errors\n", errors);
++
++do_ds250dfx10_pttchk_validate_cdr_lock_loss_int:
++ /* disable cdr lock loss indication */
++ ds250dfx10_set(DS250DFX10_CDR_LOCK_LOSS_INT_EN, 0);
++
++do_ds250dfx10_pttchk_validate_prbs_int:
++ /* disable prbs interrupts */
++ ds250dfx10_set(DS250DFX10_PRBS_INT_EN, 0);
++
++do_ds250dfx10_pttchk_validate_ret:
++ return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
++}
++
+ static int do_ds250dfx10_pttchk(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+ {
+ int ret;
+@@ -663,19 +851,25 @@ static int do_ds250dfx10_pttchk(struct cmd_tbl *cmdtp, int flag, int argc, char
+ return CMD_RET_FAILURE;
+ }
+
+- if (argc != 2)
+- return CMD_RET_USAGE;
++ if (argc == 2 && !strcmp(argv[1], "start")) {
++ ret = ds250dfx10_pttchk_enable();
++ if (ret)
++ return CMD_RET_FAILURE;
+
+- if (!strcmp(argv[1], "show"))
+- ret = do_ds250dfx10_pttchk_show();
+- else if (!strcmp(argv[1], "start"))
+- ret = do_ds250dfx10_pttchk_start();
+- else if (!strcmp(argv[1], "stop"))
+- ret = do_ds250dfx10_pttchk_stop();
+- else
+- return CMD_RET_USAGE;
++ ret = ds250dfx10_pttchk_reset();
++ if (ret)
++ return CMD_RET_FAILURE;
+
+- return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
++ return CMD_RET_SUCCESS;
++ } else if (argc == 2 && !strcmp(argv[1], "detect")) {
++ return do_ds250dfx10_pttchk_detect(1 * 1000 /* timeout 1 second */);
++ } else if (argc == 3 && !strcmp(argv[1], "validate")) {
++ return do_ds250dfx10_pttchk_validate(simple_strtol(argv[2], NULL, 0));
++ } else if (argc == 2 && !strcmp(argv[1], "stop")) {
++ return ds250dfx10_pttchk_disable() ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
++ } else {
++ return CMD_RET_USAGE;
++ }
+ }
+
+ /* read data bytes and dump as csv */
+@@ -784,64 +978,58 @@ static int do_ds250dfx10_eom(struct cmd_tbl *cmdtp, int flag, int argc, char *co
+ return CMD_RET_FAILURE;
+ }
+
+- /* enable access to channel registers */
+- ret = ds250dfx10_set(DS250DFX10_EN_CH_SMB, 1);
+- if (ret)
+- goto do_ds250dfx10_eom_ret;
+-
+ /* test if CDR locked */
+ ret = ds250dfx10_get(DS250DFX10_CDR_LOCK_STATUS, &val1);
+ if (ret)
+- goto do_ds250dfx10_eom_cleanup;
++ return ret;
+ else if (!val1) {
+ puts("cdr not locked, ensure pattern generator is active and connected\n");
+- ret = -EIO;
+- goto do_ds250dfx10_eom_cleanup;
++ return -EIO;
+ }
+
+ /* disable lock monitoring */
+ ret = ds250dfx10_set(DS250DFX10_HV_LOCKMON_EN, 0);
+ if (ret)
+- goto do_ds250dfx10_eom_cleanup;
++ goto do_ds250dfx10_eom_lockmon;
+
+ /* disable automatic vertical range scaling */
+ ret = ds250dfx10_set(DS250DFX10_VEO_SCALE, 0);
+ if (ret)
+- goto do_ds250dfx10_eom_cleanup;
++ goto do_ds250dfx10_eom_lockmon;
+
+ /* set vertical range */
+ ret = ds250dfx10_set(DS250DFX10_EOM_SEL_VRANGE, vrange);
+ if (ret)
+- goto do_ds250dfx10_eom_cleanup;
++ goto do_ds250dfx10_eom_vrange;
+
+ /* force enable eom */
+ ret = ds250dfx10_set(DS250DFX10_EOM_PD, 0);
+ if (ret)
+- goto do_ds250dfx10_eom_cleanup;
++ goto do_ds250dfx10_eom_vrange;
+
+ /* enable eom fast mode */
+ ret = ds250dfx10_set(DS250DFX10_FAST_EOM, 1);
+ if (ret)
+- goto do_ds250dfx10_eom_cleanup;
++ goto do_ds250dfx10_eom_pd;
+
+ /* read eye diagram */
+ /* (re-)start counter */
+ ret = ds250dfx10_set(DS250DFX10_EOM_START, 1);
+ if (ret)
+- goto do_ds250dfx10_eom_cleanup;
++ goto do_ds250dfx10_eom_fast;
+
+ /* wait for eom capture to complete */
+ do {
+ ret = ds250dfx10_get(DS250DFX10_EOM_START, &val1);
+ if (ret)
+- goto do_ds250dfx10_eom_cleanup;
++ goto do_ds250dfx10_eom_fast;
+ } while (val1);
+
+ /* skip first 4 invalid data bytes */
+ for (int i = 0; i < 4; i++) {
+ ret = ds250dfx10_read(DS250DFX10_EOM_DATA_HI, (uint8_t *)&val2, sizeof(val2));
+ if (ret)
+- goto do_ds250dfx10_eom_cleanup;
++ goto do_ds250dfx10_eom_fast;
+ }
+
+ switch (fmt) {
+@@ -856,25 +1044,24 @@ static int do_ds250dfx10_eom(struct cmd_tbl *cmdtp, int flag, int argc, char *co
+ break;
+ }
+ if (ret)
+- goto do_ds250dfx10_eom_cleanup;
++ goto do_ds250dfx10_eom_fast;
+
++do_ds250dfx10_eom_fast:
+ /* disable eom fast mode */
+- ret = ds250dfx10_set(DS250DFX10_FAST_EOM, 0);
++ ds250dfx10_set(DS250DFX10_FAST_EOM, 0);
+
++do_ds250dfx10_eom_pd:
+ /* return eom to automatic mode */
+- ret = ds250dfx10_set(DS250DFX10_EOM_PD, 1);
++ ds250dfx10_set(DS250DFX10_EOM_PD, 1);
+
++do_ds250dfx10_eom_vrange:
+ /* (re-)enable automatic vrange scaling */
+- ret = ds250dfx10_set(DS250DFX10_VEO_SCALE, 1);
++ ds250dfx10_set(DS250DFX10_VEO_SCALE, 1);
+
++do_ds250dfx10_eom_lockmon:
+ /* (re-)enable lock monitoring */
+- ret = ds250dfx10_set(DS250DFX10_HV_LOCKMON_EN, 0);
+-
+-do_ds250dfx10_eom_cleanup:
+- /* disable access to channel registers */
+- ds250dfx10_set(DS250DFX10_EN_CH_SMB, 0);
++ ds250dfx10_set(DS250DFX10_HV_LOCKMON_EN, 0);
+
+-do_ds250dfx10_eom_ret:
+ return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+ }
+
+@@ -896,10 +1083,11 @@ static int do_ds250dfx10_todo(struct cmd_tbl *cmdtp, int flag, int argc, char *c
+ *
+ * => ds250dfx10 dev i2c at 2020000 0x18
+ * => ds250dfx10 chan 0
+- * => ds250dfx10 pttgen PRBS7
++ * => ds250dfx10 pttgen PRBS31
+ * => ds250dfx10 chan 1
+ * => ds250dfx10 pttchk start
+- * => ds250dfx10 pttchk show
++ * => ds250dfx10 pttchk detect
++ * => ds250dfx10 pttchk validate 10
+ * => ds250dfx10 eom VTE
+ */
+
+@@ -909,8 +1097,9 @@ U_BOOT_LONGHELP(ds250dfx10,
+ "ds250dfx10 pttgen <pattern> - start pattern generator\n"
+ " - <pattern> is one of [ PRBS7, PRBS9, PRBS11, PRBS15, PRBS23, PRBS31, PRBS58, PRBS63]\n"
+ "ds250dfx10 pttgen stop - stop pattern generator\n"
+- "ds250dfx10 pttchk show - print pattern checker results\n"
+ "ds250dfx10 pttchk start - start pattern checker\n"
++ "ds250dfx10 pttchk detect - try detect current pattern\n"
++ "ds250dfx10 pttchk validate <duration> - detect and validate current pattern for <duration> seconds\n"
+ "ds250dfx10 pttchk stop - stop pattern checker\n"
+ "ds250dfx10 eom <format> - capture eye diagram\n"
+ " <format> is one of [ CSV, VTE ]\n"
+@@ -922,6 +1111,6 @@ U_BOOT_CMD_WITH_SUBCMDS(ds250dfx10, "DS250DFx10 Retimer", ds250dfx10_help_text,
+ U_BOOT_SUBCMD_MKENT(dev, 3, 1, do_ds250dfx10_dev),
+ U_BOOT_SUBCMD_MKENT(chan, 2, 1, do_ds250dfx10_chan),
+ U_BOOT_SUBCMD_MKENT(pttgen, 2, 1, do_ds250dfx10_pttgen),
+- U_BOOT_SUBCMD_MKENT(pttchk, 2, 1, do_ds250dfx10_pttchk),
++ U_BOOT_SUBCMD_MKENT(pttchk, 3, 1, do_ds250dfx10_pttchk),
+ U_BOOT_SUBCMD_MKENT(eom, 2, 1, do_ds250dfx10_eom),
+ U_BOOT_SUBCMD_MKENT(todo, 100, 1, do_ds250dfx10_todo));
+--
+2.51.0
+
diff --git a/board/solidrun/lx2160acex7/post-build.sh b/board/solidrun/lx2160acex7/post-build.sh
new file mode 100755
index 0000000000..0602fa5762
--- /dev/null
+++ b/board/solidrun/lx2160acex7/post-build.sh
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+BOARD_DIR="$(dirname $0)"
+PARTUUID="$($HOST_DIR/bin/uuidgen)"
+
+install -d "$TARGET_DIR/boot/extlinux/"
+sed "s/%PARTUUID%/$PARTUUID/g" "$BOARD_DIR/extlinux.conf" > "$TARGET_DIR/boot/extlinux/extlinux.conf"
+sed "s/%PARTUUID%/$PARTUUID/g" "$BOARD_DIR/genimage.cfg" > "$BINARIES_DIR/genimage.cfg"
diff --git a/board/solidrun/lx2160acex7/readme.txt b/board/solidrun/lx2160acex7/readme.txt
new file mode 100644
index 0000000000..5e676301ca
--- /dev/null
+++ b/board/solidrun/lx2160acex7/readme.txt
@@ -0,0 +1,136 @@
+*********************
+SolidRun LX2160A-CEx7
+*********************
+
+This file documents the Buildroot support for the NXP Layerscape CEx7 LX2160A
+board made by SolidRun. The CEx7 (COM Express type 7) is a Computer On Module
+which can be plugged into different carrier boards. It is sold either
+separately, or with the HoneyComb LX2 or Clearfog CX LX2 carrier boards, both
+having Mini ITX form factors.
+
+Both the HoneyComb LX2 and Clearfog CX LX2 carrier boards are targeted towards
+networking use cases, with 4 10G-capable SFP+ cages, and the Clearfog
+additionally having a 4x25G-capable QSFP28 cage. In addition, the carrier
+boards have 4x SATA III interfaces, PCIe Gen 3 x8, 2x USB 3.0, an m.2 slot
+compatible with NVMe SSDs, pin headers for traditional PC/NAS cases, and
+regular RJ45 1G Ethernet.
+
+The developer resources for the platform can be found at:
+ - https://solidrun.atlassian.net/wiki/spaces/developer/pages/197493977/NXP+LX2160A+Based+Products
+
+SolidRun keeps build scripts for the firmware on GitHub, which track NXP Linux
+Factory (LF) releases in the form of patches:
+ - https://github.com/SolidRun/lx2160a_build
+
+The most recent functional branch is develop-ls-5.15.71-2.2.0. These patches
+are also included into Buildroot, except for the Linux kernel, where the most
+recent lf-6.6.36-2.1.0 NXP tag is used directly.
+
+The Buildroot support is for the maximal configuration, which is the CEX7
+platform on the Clearfog CX LX2 carrier board.
+
+Set DDR
+=======
+
+At boot, the LX2160 programs its DDR controller from the RCW.
+Select the RCW matching the maximum DDR performance.
+Update the following configuration options:
+
+ BR2_PACKAGE_HOST_QORIQ_RCW_INTREE="lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw"
+
+where 2600 is for a DDR4 2666.
+
+If you do have the proper settings, you'll likely face such error:
+
+ NOTICE: BL2: v2.10.0 (release):custom
+ NOTICE: BL2: Built : 01:06:19, Sep 4 2025
+ NOTICE: UDIMM TIMETEC-ESD4-2666
+ ERROR: DDR Clk: MCLK cycle is 625 ps.
+ ERROR: DDR Clk is faster than DIMM can support.
+ ERROR: cas latency is too large 41
+ ERROR: Calculating DDR registers failed
+ ERROR: Calculate register error
+ ERROR: DDR init failed.
+ ERROR: Asserting as the DDR is not initialized yet.
+
+Build
+=====
+
+First, configure Buildroot for the LX2160A-CEX7 platform:
+
+ make solidrun_lx2160acex7_defconfig
+
+Build all components:
+
+ make
+
+You will find in output/images/ the following files:
+ - bl2_sd.pbl - RCW + ATF BL2 stage
+ - dpc.dtb
+ - dpl.dtb
+ - fip.bin - U-Boot packaged as ATF payload
+ - fip_ddr.bin - DDR PHY firmware
+ - fsl-lx2160a-clearfog-cx.dtb
+ - fsl-lx2160a-honeycomb.dtb
+ - Image
+ - mc.itb - MC firmware
+ - PBL.bin
+ - rootfs.ext2
+ - rootfs.ext4
+ - sdcard.img
+ - u-boot.bin
+ - uboot-env.bin
+
+Create a bootable SD card
+=========================
+
+To determine the device associated to the SD card have a look in the
+/proc/partitions file:
+
+ cat /proc/partitions
+
+Buildroot prepares a bootable "sdcard.img" image in the output/images/
+directory, ready to be dumped on a SD card. Launch the following
+command as root:
+
+ dd if=output/images/sdcard.img of=/dev/sdX
+
+*** WARNING! This will destroy all the card content. Use with care! ***
+
+For details about the medium image layout, see the definition in
+board/solidrun/lx2160acex7/genimage.cfg.
+
+Boot the LX2160A-CEX7 board
+===========================
+
+To boot your newly created system:
+- configure the DIP switches for SD boot selection as per SolidRun instructions:
+ https://solidrun.atlassian.net/wiki/spaces/developer/pages/197494288/HoneyComb+LX2+ClearFog+CX+LX2+Quick+Start+Guide#Boot-Select
+- insert the Micro-SD card in the Micro-SD slot of the board
+- put a Micro-USB cable into the Micro-USB connector labeled CONSOLE (CON9)
+ and connect using a terminal emulator at 115200 bps, 8n1.
+- power on the board.
+
+The DPL file only contains a static description for the 1G RGMII RJ45 port
+(endpmac17). By default, this will attempt acquire an IP address over DHCP.
+
+The 4 interfaces routed to the SFP+ cages are endpmac7, endpmac8, endpmac9 and
+endpmac10. Among the more usual networking choices, one could create individual
+DPNIs for each MAC:
+
+$ ls-addni dpmac.7 && ls-addni dpmac.8 && ls-addni dpmac.9 && ls-addni dpmac.10
+
+or a DPSW object to accelerate L2 forwarding between them:
+
+$ ls-addsw --num-ifs=4 --max-fdbs=4 --flooding-cfg=DPSW_FLOODING_PER_FDB \
+ --broadcast-cfg=DPSW_BROADCAST_PER_FDB dpmac.7 dpmac.8 dpmac.9 dpmac.10
+$ ip link add br0 type bridge vlan_filtering 1 && ip link set br0 up
+$ for eth in endpmac7 endpmac8 endpmac9 endpmac10; do \
+ ip link set $eth master br0 && ip link set $eth up; done
+
+Once the runtime configuration is satisfactory, it can be converted back into a
+permanent DPL file which can be plugged back into the build system:
+
+$ restool dprc generate-dpl > dpl-new.dts
+
+Networking options through the QSFP28 cage have not yet been investigated.
diff --git a/board/solidrun/lx2160acex7/rootfs_overlay/etc/udev/rules.d/74-dpaa2-networking.rules b/board/solidrun/lx2160acex7/rootfs_overlay/etc/udev/rules.d/74-dpaa2-networking.rules
new file mode 100644
index 0000000000..5265d6b489
--- /dev/null
+++ b/board/solidrun/lx2160acex7/rootfs_overlay/etc/udev/rules.d/74-dpaa2-networking.rules
@@ -0,0 +1,12 @@
+SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc at 80c000000/dpmacs/ethernet at 1", NAME="endpmac1"
+SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc at 80c000000/dpmacs/ethernet at 2", NAME="endpmac2"
+SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc at 80c000000/dpmacs/ethernet at 3", NAME="endpmac3"
+SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc at 80c000000/dpmacs/ethernet at 4", NAME="endpmac4"
+SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc at 80c000000/dpmacs/ethernet at 5", NAME="endpmac5"
+SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc at 80c000000/dpmacs/ethernet at 6", NAME="endpmac6"
+SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc at 80c000000/dpmacs/ethernet at 7", NAME="endpmac7"
+SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc at 80c000000/dpmacs/ethernet at 8", NAME="endpmac8"
+SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc at 80c000000/dpmacs/ethernet at 9", NAME="endpmac9"
+SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc at 80c000000/dpmacs/ethernet at a", NAME="endpmac10"
+SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc at 80c000000/dpmacs/ethernet at 11", NAME="endpmac17"
+SUBSYSTEM=="net", ACTION=="add|change|online|offline|change", DRIVERS=="fsl_dpaa2_eth|fsl_dpaa2_switch", ENV{OF_FULLNAME}=="/soc/fsl-mc at 80c000000/dpmacs/ethernet at 12", NAME="endpmac18"
diff --git a/board/solidrun/lx2160acex7/u-boot-environment-sd.txt b/board/solidrun/lx2160acex7/u-boot-environment-sd.txt
new file mode 100644
index 0000000000..6435207e44
--- /dev/null
+++ b/board/solidrun/lx2160acex7/u-boot-environment-sd.txt
@@ -0,0 +1,96 @@
+BOARD=lx2160acex7
+arch=arm
+baudrate=115200
+board=lx2160a
+board_name=lx2160a
+boot_a_script=load ${devtype} ${devnum}:${distro_bootpart} ${scriptaddr} ${prefix}${script}; env exists secureboot && load ${devtype} ${devnum}:${distro_bootpart} ${scripthdraddr} ${prefix}${boot_script_hdr} && esbc_validate ${scripthdraddr};source ${scriptaddr}
+boot_efi_binary=load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} efi/boot/bootaa64.efi; if fdt addr ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r};else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi
+boot_efi_bootmgr=if fdt addr ${fdt_addr_r}; then bootefi bootmgr ${fdt_addr_r};else bootefi bootmgr;fi
+boot_extlinux=sysboot ${devtype} ${devnum}:${distro_bootpart} any ${scriptaddr} ${prefix}${boot_syslinux_conf}
+boot_net_usb_start=usb start
+boot_pci_enum=pci enum
+boot_prefixes=/ /boot/
+boot_script_dhcp=boot.scr.uimg
+boot_scripts=boot.scr.uimg boot.scr
+boot_syslinux_conf=extlinux/extlinux.conf
+boot_targets=usb0 mmc0 mmc1 scsi0 nvme0 dhcp
+bootargs=console=ttyAMA0,115200 earlycon=pl011,mmio32,0x21c0000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf cma=256M iommu.passthrough=1 arm-smmu.disable_bypass=0
+bootcmd=run distro_bootcmd
+bootcmd_dhcp=setenv devtype dhcp; run boot_net_usb_start; run boot_pci_enum; if dhcp ${scriptaddr} ${boot_script_dhcp}; then source ${scriptaddr}; fi;setenv efi_fdtfile ${fdtfile}; setenv efi_old_vci ${bootp_vci};setenv efi_old_arch ${bootp_arch};setenv bootp_vci PXEClient:Arch:00011:UNDI:003000;setenv bootp_arch 0xb;if dhcp ${kernel_addr_r}; then tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};if fdt addr ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r}; else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi;fi;setenv bootp_vci ${efi_old_vci};setenv bootp_arch ${efi_old_arch};setenv efi_fdtfile;setenv efi_old_arch;setenv efi_old_vci;
+bootcmd_mmc0=devnum=0; run mmc_boot
+bootcmd_mmc1=devnum=1; run mmc_boot
+bootcmd_nvme0=devnum=0; run nvme_boot
+bootcmd_scsi0=devnum=0; run scsi_boot
+bootcmd_usb0=devnum=0; run usb_boot
+bootdelay=10
+console=ttyAMA0,115200
+cpu=armv8
+distro_bootcmd=scsi_need_init=; setenv nvme_need_init; for target in ${boot_targets}; do run bootcmd_${target}; done
+efi_dtb_prefixes=/ /dtb/ /dtb/current/
+emmc_bootcmd=echo Trying load from emmc card..;mmc dev 1; mmcinfo; mmc read $load_addr $kernel_addr_sd $kernel_size_sd ;env exists secureboot && mmc read $kernelheader_addr_r $kernelhdr_addr_sd $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm $load_addr#$BOARD
+eth10addr=00:11:22:44:11:4E
+eth11addr=00:11:22:44:11:4F
+eth12addr=00:11:22:44:11:50
+eth13addr=00:11:22:44:11:51
+eth14addr=00:11:22:44:11:52
+eth15addr=00:11:22:44:11:53
+eth1addr=00:11:22:44:11:45
+eth2addr=00:11:22:44:11:46
+eth3addr=00:11:22:44:11:47
+eth4addr=00:11:22:44:11:48
+eth5addr=00:11:22:44:11:49
+eth6addr=00:11:22:44:11:4A
+eth7addr=00:11:22:44:11:4B
+eth8addr=00:11:22:44:11:4C
+eth9addr=00:11:22:44:11:4D
+ethaddr=00:11:22:44:11:44
+ethprime=DPMAC17 at rgmii-id
+fdt_addr=0x81000000
+fdt_addr_r=0x81000000
+fdt_high=0xa0000000
+fdtfile=fsl-lx2160a-cex7.dtb
+fdtheader_addr_r=0x80100000
+hwconfig=fsl_ddr:bank_intlv=auto
+initrd_high=0xffffffffffffffff
+kernel_addr_r=0x81100000
+kernel_addr_sd=0x8000
+kernel_comp_addr_r=0x9f000000
+kernel_comp_size=0x10000000
+kernel_size=0x2800000
+kernel_size_sd=0x14000
+kernel_start=0x1000000
+kernelhdr_addr_sd=0x3000
+kernelhdr_size_sd=0x20
+kernelheader_addr_r=0x80200000
+kernelheader_size=0x40000
+kernelheader_start=0x600000
+load_addr=0xa0000000
+load_efi_dtb=load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${prefix}${efi_fdtfile}
+lx2160acex7_vdd_mv=800
+dpl_addr_r=0x80d00000
+mc_fw_addr_r=0x80a00000
+dpc_addr_r=0x80e00000
+mcinitcmd=mmcinfo && mmc read $mc_fw_addr_r 0x5000 0x1200 && mmc read $dpc_addr_r 0x7000 0x800 && mmc read $dpl_addr_r 0x6800 0x800 && fsl_mc start mc $mc_fw_addr_r $dpc_addr_r && fsl_mc lazyapply dpl $dpl_addr_r
+mcmemsize=0x70000000
+fsl_bootcmd_mcinitcmd_set=y
+mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi
+nvme_boot=run boot_pci_enum; run nvme_init; if nvme dev ${devnum}; then devtype=nvme; run scan_dev_for_boot_part; fi
+nvme_init=if ${nvme_need_init}; then setenv nvme_need_init false; nvme scan; fi
+nvme_need_init=true
+ramdisk_addr=0x85100000
+ramdisk_addr_r=0x85100000
+ramdisk_size=0x2000000
+scan_dev_for_boot=echo Scanning ${devtype} ${devnum}:${distro_bootpart}...; for prefix in ${boot_prefixes}; do run scan_dev_for_extlinux; run scan_dev_for_scripts; done;run scan_dev_for_efi;
+scan_dev_for_boot_part=part list ${devtype} ${devnum} devplist; env exists devplist || setenv devplist 1; for distro_bootpart in ${devplist}; do if fstype ${devtype} ${devnum}:${distro_bootpart} bootfstype; then run scan_dev_for_boot; fi; done
+scan_dev_for_efi=setenv efi_fdtfile ${fdtfile}; for prefix in ${efi_dtb_prefixes}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${efi_fdtfile}; then run load_efi_dtb; fi;done;run boot_efi_bootmgr;if test -e ${devtype} ${devnum}:${distro_bootpart} efi/boot/bootaa64.efi; then echo Found EFI removable media binary efi/boot/bootaa64.efi; run boot_efi_binary; echo EFI LOAD FAILED: continuing...; fi; setenv efi_fdtfile
+scan_dev_for_extlinux=if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${boot_syslinux_conf}; then echo Found ${prefix}${boot_syslinux_conf}; run boot_extlinux; echo SCRIPT FAILED: continuing...; fi
+scan_dev_for_scripts=for script in ${boot_scripts}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${script}; then echo Found U-Boot script ${prefix}${script}; run boot_a_script; echo SCRIPT FAILED: continuing...; fi; done
+scriptaddr=0x80000000
+scripthdraddr=0x80080000
+scsi_boot=run scsi_init; if scsi dev ${devnum}; then devtype=scsi; run scan_dev_for_boot_part; fi
+scsi_init=if ${scsi_need_init}; then scsi_need_init=false; scsi scan; fi
+sd_bootcmd=echo Trying load from sd card..;mmcinfo; mmc read $load_addr $kernel_addr_sd $kernel_size_sd ;env exists secureboot && mmc read $kernelheader_addr_r $kernelhdr_addr_sd $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm $load_addr#$BOARD
+soc=fsl-layerscape
+usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi
+vendor=solidrun
+xspi_bootcmd=echo Trying load from flexspi..;sf probe 0:0 && sf read $load_addr $kernel_start $kernel_size ; env exists secureboot &&sf read $kernelheader_addr_r $kernelheader_start $kernelheader_size && esbc_validate ${kernelheader_addr_r}; bootm $load_addr#$BOARD
diff --git a/configs/solidrun_lx2160acex7_defconfig b/configs/solidrun_lx2160acex7_defconfig
new file mode 100644
index 0000000000..9ab01fd68d
--- /dev/null
+++ b/configs/solidrun_lx2160acex7_defconfig
@@ -0,0 +1,53 @@
+BR2_aarch64=y
+BR2_cortex_a72=y
+BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_6=y
+BR2_GLOBAL_PATCH_DIR="board/solidrun/lx2160acex7/patches"
+BR2_TARGET_GENERIC_HOSTNAME="lx2160acex7"
+BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV=y
+BR2_TARGET_GENERIC_GETTY_PORT="ttyAMA0"
+BR2_ROOTFS_OVERLAY="board/solidrun/lx2160acex7/rootfs_overlay"
+BR2_ROOTFS_POST_BUILD_SCRIPT="board/solidrun/lx2160acex7/post-build.sh"
+BR2_ROOTFS_POST_IMAGE_SCRIPT="support/scripts/genimage.sh"
+BR2_ROOTFS_POST_SCRIPT_ARGS="-c $(BINARIES_DIR)/genimage.cfg"
+BR2_LINUX_KERNEL=y
+BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
+BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,linux,lf-6.6.52-2.2.0)/linux-lf-6.6.52-2.2.0.tar.gz"
+BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG=y
+BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(LINUX_DIR)/arch/arm64/configs/lsdk.config board/solidrun/lx2160acex7/linux.config"
+BR2_LINUX_KERNEL_DTS_SUPPORT=y
+BR2_LINUX_KERNEL_INTREE_DTS_NAME="freescale/fsl-lx2160a-clearfog-cx freescale/fsl-lx2160a-honeycomb"
+BR2_LINUX_KERNEL_INSTALL_TARGET=y
+BR2_PACKAGE_QORIQ_DDR_PHY_BINARY=y
+BR2_PACKAGE_QORIQ_MC_BINARY=y
+BR2_PACKAGE_QORIQ_MC_BINARY_TARGET_LX2160A=y
+BR2_PACKAGE_QORIQ_MC_UTILS=y
+BR2_PACKAGE_QORIQ_MC_UTILS_DPC_CUSTOM_PATH="board/solidrun/lx2160acex7/clearfog-cx-s1_8-s2_0-dpc"
+BR2_PACKAGE_QORIQ_MC_UTILS_DPL_CUSTOM_PATH="board/solidrun/lx2160acex7/clearfog-cx-s1_8-s2_0-dpl"
+BR2_PACKAGE_QORIQ_MC_UTILS_TARGET_INSTALL_PATH="usr/share/mc/"
+BR2_PACKAGE_QORIQ_RESTOOL=y
+BR2_TARGET_ROOTFS_CPIO=y
+BR2_TARGET_ROOTFS_EXT2=y
+BR2_TARGET_ROOTFS_EXT2_4=y
+BR2_TARGET_ROOTFS_EXT2_SIZE="130M"
+BR2_TARGET_ARM_TRUSTED_FIRMWARE=y
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL=y
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,atf,lf-6.6.52-2.2.0)/atf-lf-6.6.52-2.2.0.tar.gz"
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="lx2160acex7"
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_FIP=y
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_UBOOT_AS_BL33=y
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_RCW=y
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_ADDITIONAL_VARIABLES="BOOT_MODE=sd"
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_IMAGES="fip.bin bl2_sd.pbl"
+BR2_TARGET_UBOOT=y
+BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
+BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
+BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,nxp-qoriq,u-boot,lf-6.6.52-2.2.0)/u-boot-lf-6.6.52-2.2.0.tar.gz"
+BR2_TARGET_UBOOT_BOARD_DEFCONFIG="lx2160acex7_tfa"
+BR2_TARGET_UBOOT_NEEDS_DTC=y
+BR2_PACKAGE_HOST_GENIMAGE=y
+BR2_PACKAGE_HOST_QORIQ_RCW=y
+BR2_PACKAGE_HOST_QORIQ_RCW_INTREE="lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw"
+BR2_PACKAGE_HOST_UBOOT_TOOLS=y
+BR2_PACKAGE_HOST_UBOOT_TOOLS_ENVIMAGE=y
+BR2_PACKAGE_HOST_UBOOT_TOOLS_ENVIMAGE_SOURCE="board/solidrun/lx2160acex7/u-boot-environment-sd.txt"
+BR2_PACKAGE_HOST_UBOOT_TOOLS_ENVIMAGE_SIZE="0x2000"
--
2.34.1
More information about the buildroot
mailing list